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71. 发明授权

US07542325B2 Ferroelectric memory 失效
标题翻译：铁电存储器
公开(公告)号：US07542325B2
公开(公告)日：2009-06-02
申请号：US11873764
申请日：2007-10-17
申请人： Tadashi Miyakawa , Daisaburo Takashima
发明人： Tadashi Miyakawa , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： A ferroelectric memory comprises a memory cell block of plural serially connected memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel therewith. And the ferroelectric memory comprises a cell transistor resistance measuring circuit, a word line voltage controller, and a word line voltage generator. The cell transistor resistance measuring circuit measures a resistance of the cell transistor. The word line voltage controller controls a word line voltage applied to a gate of the cell transistor based on the resistance of the cell transistor. The word line voltage generator generates the word line voltage.
摘要翻译：铁电存储器包括多个串联存储单元的存储单元块，每个存储单元包括与其并联连接的单元晶体管和铁电电容器。并且铁电存储器包括单元晶体管电阻测量电路，字线电压控制器和字线电压发生器。单元晶体管电阻测量电路测量单元晶体管的电阻。字线电压控制器基于单元晶体管的电阻来控制施加到单元晶体管的栅极的字线电压。字线电压发生器产生字线电压。

72. 发明申请

US20090040807A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090040807A1
公开(公告)日：2009-02-12
申请号：US12186088
申请日：2008-08-05
申请人： Sumiko DOUMAE , Daisaburo Takashima
发明人： Sumiko DOUMAE , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： A semiconductor memory device comprises a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.
摘要翻译：半导体存储器件包括存储单元阵列，每个存储单元包括单元晶体管和铁电电容器; 感测放大器电路，用于通过一对位线来感测/放大从铁电电容器读出的信号; 一对去耦晶体管，设置在该对位线上以去耦合位线; 控制电路，用于向去耦晶体管的栅极提供控制信号，以控制去耦晶体管的导通; 以及与去耦晶体管和感测放大器电路之间的一对位线中的至少一个相关联地设置的虚拟电容器。控制电路被配置为能够在读取开始之后经过一段时间后，使去耦晶体管从导通断开。

73. 发明授权

US07426147B2 Power supply voltage control circuit 失效
标题翻译：电源电压控制电路
公开(公告)号：US07426147B2
公开(公告)日：2008-09-16
申请号：US11531163
申请日：2006-09-12
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/22
摘要： A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit lines, includes a word line control circuit for supplying a first voltage to the word lines; and a plate line control circuit for supplying a second voltage to the plate lines; and the power supply voltage control circuit provides an amount of current flow from the first voltage so as to keep the first voltage potential almost constant during increasing a value of the second voltage in a power-on sequence, firstly increasing a value of the higher voltage of two potential voltages: the first voltage and the second voltage capacitive coupled, and then increasing a value of the lower second voltage.
摘要翻译： 1.一种电源电压控制电路，其向存储单元阵列供给电源电压，所述电源电压包括沿着行方向延伸的字线，沿着列方向延伸的位线，沿着行方向延伸的板条，以及设置在字线和位线包括用于向字线提供第一电压的字线控制电路; 以及板线控制电路，用于向所述板线提供第二电压; 并且电源电压控制电路提供从第一电压的电流量，以便在增加通电序列中的第二电压的值时，保持第一电压电位几乎恒定，首先增加较高电压的值的两个电位电压：第一电压和第二电压电容耦合，然后增加较低的第二电压的值。

74. 发明申请

US20080191792A1 VOLTAGE GENERATING CIRCUIT 有权
标题翻译：电压发生电路
公开(公告)号：US20080191792A1
公开(公告)日：2008-08-14
申请号：US12027699
申请日：2008-02-07
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： Disclosed is a voltage generating circuit which steps down a voltage to output a stepped down voltage. The voltage generating circuit includes first and second transistors. The drains of the first and second transistors are connected to a higher voltage power supply. The gate of the first transistor is connected to the gate of the second transistor. The voltage of the gate of the first transistor is controlled by a control circuit such that a voltage of the source of the first transistor can reach a predetermined voltage. A stepped down voltage is outputted from the source of the second transistor.
摘要翻译：公开了一种降压电压以输出降压的电压产生电路。电压产生电路包括第一和第二晶体管。第一和第二晶体管的漏极连接到较高电压的电源。第一晶体管的栅极连接到第二晶体管的栅极。第一晶体管的栅极的电压由控制电路控制，使得第一晶体管的源极的电压可以达到预定电压。从第二晶体管的源极输出降压电压。

75. 发明授权

US07379319B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07379319B2
公开(公告)日：2008-05-27
申请号：US11775680
申请日：2007-07-10
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate.
摘要翻译：半导体集成电路器件包括半导体衬底和设置在半导体衬底的表面上的多个单元晶体管。局部位线设置在单元晶体管的上方并电连接到每个单元晶体管的源极扩散层和漏极扩散层之一。对应于单元晶体管的铁电电容器设置在局部位线上方，其中每个强电介质电容器具有电连接到相应的源极扩散层和漏极扩散层中的另一个的上电极和下电极一个单元晶体管。在上电极上方设置有电镀线，与上电极电连接。复位晶体管和块选择晶体管设置在半导体衬底的表面上。

76. 发明申请

US20080111575A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080111575A1
公开(公告)日：2008-05-15
申请号：US11937056
申请日：2007-11-08
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G01R31/27
CPC分类号： G01R31/3004 , G11C29/12005 , G11C29/50
摘要： According to an aspect of the invention, there is provided, a semiconductor device, including an internal voltage generation circuit generating a prescribed voltage, a first test circuit connecting to a voltage-supplying wiring, one end of the voltage-supplying wiring being connected to a source wiring and the other end of the voltage-supplying wiring being connected to the internal voltage generation circuit, the first test circuit being supplied an outer voltage from the source wiring and a voltage of the internal voltage generation circuit through the voltage-supplying wiring, the first test circuit generating a prescribed resistance value on a basis of a control input from an outer portion in a test mode.
摘要翻译：根据本发明的一个方面，提供了一种半导体器件，包括产生规定电压的内部电压产生电路，连接到电压供给布线的第一测试电路，所述电压供给布线的一端连接到源极布线和电压供给布线的另一端连接到内部电压产生电路，第一测试电路通过电压布线从源极布线提供外部电压和内部电压产生电路的电压，所述第一测试电路基于来自测试模式中的外部的控制输入而产生规定的电阻值。

77. 发明申请

US20080084730A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080084730A1
公开(公告)日：2008-04-10
申请号：US11902873
申请日：2007-09-26
申请人： Katsuhiko Hoya , Daisaburo Takashima
发明人： Katsuhiko Hoya , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.
摘要翻译：存储单元阵列包括存储单元，存储单元包括铁电电容器和晶体管。存储单元阵列包括选择存储单元的字线，向铁电电容器施加驱动电压的板线和从铁电电容器读取数据的位线。选择晶体管选择性地将存储单元连接到位线。虚拟单元提供参考电位，参考电位参考从存储单元读取的电位。读出放大器电路包括放大位线对之间的电位差的多个放大电路。去耦电路电切断放大电路之间的位线。

78. 发明授权

US07295456B2 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor 有权
标题翻译：具有与铁电电容器并联连接的本征晶体管的链式铁电随机存取存储器（CFRAM）
公开(公告)号：US07295456B2
公开(公告)日：2007-11-13
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

79. 发明授权

US07269048B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07269048B2
公开(公告)日：2007-09-11
申请号：US10988673
申请日：2004-11-16
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes a plurality of first memory cells each of which includes a cell transistor whose gate terminal is connected to a word line and a ferroelectric capacitor which is connected at one end to a source terminal of the cell transistor. The drain terminals of the cell transistors of are used as a first local bit line, the other end of each of the ferroelectric capacitors are used as a first plate line. A first reset transistor has a source terminal connected to the first plate line and a drain terminal connected to the first local bit line. A first block selection transistor has a source terminal connected to the first local bit line and a drain terminal connected to a first bit line.
摘要翻译：半导体集成电路器件包括多个第一存储单元，每个第一存储单元包括其栅极端子连接到字线的单元晶体管和一端连接到单元晶体管的源极端子的铁电电容器。单元晶体管的漏极端子用作第一局部位线，每个强电介质电容器的另一端用作第一板线。第一复位晶体管具有连接到第一板线的源极端子和连接到第一局部位线的漏极端子。第一块选择晶体管具有连接到第一局部位线的源极端子和连接到第一位线的漏极端子。

80. 发明授权

US07248493B2 Memory system having improved random write performance 有权
标题翻译：具有改进的随机写入性能的存储器系统
公开(公告)号：US07248493B2
公开(公告)日：2007-07-24
申请号：US11277706
申请日：2006-03-28
申请人： Daisaburo Takashima , Shuso Fujii , Takuya Futatsuyama , Takaya Suda , Masaki Momodomi
发明人： Daisaburo Takashima , Shuso Fujii , Takuya Futatsuyama , Takaya Suda , Masaki Momodomi
IPC分类号： G11C7/00
CPC分类号： G11C11/22 , G06F12/0246 , G06F12/0292 , G06F2212/2022 , G06F2212/7201 , G11C8/10
摘要： A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.
摘要翻译：存储系统包括铁电存储器，闪存EEPROM，控制电路和接口电路。控制电路被配置为控制铁电存储器和闪存EEPROM。接口电路被配置为从外部通信。数据通过写入单元编程在闪存EEPROM中，该写入单元比作为擦除单元的块小并且大于作为程序单元的页面。铁电存储器使用写入单元存储逻辑地址 - 物理地址转换表。

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