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1. 发明申请

US20100149850A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100149850A1
公开(公告)日：2010-06-17
申请号：US12635590
申请日：2009-12-10
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G11C11/22 , G11C7/06 , G11C5/06
CPC分类号： G11C11/22
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having series-connected memory cells; wordlines; and a bitline pair connected to the memory cell blocks, one functioning as a readout bitline, the other one functioning as a reference bitline; an amplification circuit connected to the bitline pair to amplify a signal difference therebetween; and a reference voltage generation circuit including: a dummy memory cell block that has the same configuration as the memory cell block, that has one terminal connected to a first dummy plate line and that has the other terminal connected to the reference bitline; and a paraelectric capacitor that has one terminal connected to a second dummy plate line and that has the other terminal connected to the reference bitline.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：存储单元阵列，包括：具有串联存储单元的存储单元块; 字线以及连接到存储单元块的位线对，一个用作读出位线，另一个用作参考位线; 连接到所述位线对的放大电路，以放大其间的信号差; 以及参考电压产生电路，包括：具有与所述存储单元块相同配置的虚拟存储单元块，其具有连接到第一虚设板线并且具有连接到所述参考位线的另一个端子的一个端子; 以及具有一个端子连接到第二虚拟板线并且另一个端子连接到参考位线的顺电电容器。

2. 发明申请

US20090115387A1 VOLTAGE GENERATING CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20090115387A1
公开(公告)日：2009-05-07
申请号：US12266143
申请日：2008-11-06
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G05F1/10
CPC分类号： G05F1/575 , G05F3/16 , Y10T307/50
摘要： A voltage generating circuit comprising: a switching device which includes a first end connected to a high potential side power source, and which becomes conductive in a first mode and becomes non-conductive in a second mode; a first transistor including a first main electrode connected to a second end of the switching device, a second main electrode connected to an output terminal, and a gate connected to a gate potential supply node; a second transistor including a first main electrode connected to the high potential side power source, a second main electrode connected to the output terminal, and a gate connected to the gate potential supply node; and a gate voltage stabilizing circuit that suppresses a fluctuation in potential of the potential supply node, the fluctuation accompanying a change between the first and second modes.
摘要翻译：一种电压产生电路，包括：开关装置，其包括连接到高电位侧电源的第一端，并且在第一模式中变为导通并且在第二模式中变为不导通; 第一晶体管，包括连接到开关装置的第二端的第一主电极，连接到输出端子的第二主电极和连接到栅极电位供应节点的栅极; 第二晶体管，包括连接到高电位侧电源的第一主电极，连接到输出端子的第二主电极和连接到栅极电位供应节点的栅极; 以及抑制电源供给节点的电位波动的栅极电压稳定电路，伴随着第一和第二模式之间的变化的波动。

3. 发明申请

US20110007579A1 INTERNAL VOLTAGE GENERATOR 有权
标题翻译：内部电压发生器
公开(公告)号：US20110007579A1
公开(公告)日：2011-01-13
申请号：US12835615
申请日：2010-07-13
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert a temperature characteristic voltage that changes depending on a temperature of the semiconductor memory into a second digital value. An adder is configured to receive a reference voltage trimming address that specifies the reference voltage, the first digital value, and the second digital value, and to output a third digital value obtained by performing a weighted addition of the reference voltage trimming address, the first digital value, and the second digital value. A driver is configured to output the reference voltage responding to the third digital value.
摘要翻译：根据实施例的内部电压发生器产生用于检测存储在半导体存储器中的数据的参考电压。第一AD转换器被配置为将提供给半导体存储器的外部电压转换为第一数字值。第二AD转换器被配置为将根据半导体存储器的温度而变化的温度特性电压转换为第二数字值。加法器被配置为接收指定参考电压，第一数字值和第二数字值的参考电压调整地址，并且输出通过执行参考电压调整地址的加权相加获得的第三数字值，第一数字值和第二数字值。驱动器被配置为响应于第三数字值输出参考电压。

4. 发明申请

US20100237931A1 INTERNAL POWER SUPPLY VOLTAGE GENERATION CIRCUIT 审中-公开
标题翻译：内部电源电压发生电路
公开(公告)号：US20100237931A1
公开(公告)日：2010-09-23
申请号：US12727123
申请日：2010-03-18
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G05F3/30 , H02M3/07 , H02M2003/072
摘要： An internal power supply voltage generation circuit 100 has a first charge pump circuit which steps up the external power supply voltage in response to the first clock signal and outputs a first stepped up voltage from the first voltage stepup output terminal; a second charge pump circuit which steps up the first stepup voltage in response to the second clock signal and outputs a second stepped up voltage from the second voltage stepup output terminal, the second stepped up voltage being higher than the first stepped up voltage; a first voltage stepdown circuit which steps down the first stepped up voltage and outputs a first stepped down voltage; and a second voltage stepdown circuit which steps down the second stepped up voltage and outputs a second stepped down voltage, the second stepped down voltage being higher than the first stepped up voltage.
摘要翻译：内部电源电压产生电路100具有第一电荷泵电路，其响应于第一时钟信号升高外部电源电压，并从第一升压输出端子输出第一升压电压; 第二电荷泵电路，其响应于所述第二时钟信号升高所述第一升压电压，并且从所述第二升压输出端子输出第二升压电压，所述第二升压电压高于所述第一升压电压; 降低第一升压电压并输出第一降压电压的第一降压电路; 以及第二降压电路，其降低所述第二升压电压并输出第二降压电压，所述第二降压电压高于所述第一升压电压。

5. 发明申请

US20080191792A1 VOLTAGE GENERATING CIRCUIT 有权
标题翻译：电压发生电路
公开(公告)号：US20080191792A1
公开(公告)日：2008-08-14
申请号：US12027699
申请日：2008-02-07
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： Disclosed is a voltage generating circuit which steps down a voltage to output a stepped down voltage. The voltage generating circuit includes first and second transistors. The drains of the first and second transistors are connected to a higher voltage power supply. The gate of the first transistor is connected to the gate of the second transistor. The voltage of the gate of the first transistor is controlled by a control circuit such that a voltage of the source of the first transistor can reach a predetermined voltage. A stepped down voltage is outputted from the source of the second transistor.
摘要翻译：公开了一种降压电压以输出降压的电压产生电路。电压产生电路包括第一和第二晶体管。第一和第二晶体管的漏极连接到较高电压的电源。第一晶体管的栅极连接到第二晶体管的栅极。第一晶体管的栅极的电压由控制电路控制，使得第一晶体管的源极的电压可以达到预定电压。从第二晶体管的源极输出降压电压。

6. 发明申请

US20070115007A1 POWER-ON DETECTING CIRCUIT 失效
标题翻译：上电检测电路
公开(公告)号：US20070115007A1
公开(公告)日：2007-05-24
申请号：US11558156
申请日：2006-11-09
申请人： Ryu OGIWARA , Daisaburo Takashima
发明人： Ryu OGIWARA , Daisaburo Takashima
IPC分类号： H01L35/00 , G01R27/08
CPC分类号： G01R19/16552
摘要： A circuit for detecting a power-on voltage of power supply encompasses a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, and a detecting circuit connected between the first power supply and the second power supply. The voltage divider includes a series circuit encompassing a diode, a first dividing resistor connected to the diode and a second dividing resistor connected between the first dividing resistor and the second power supply. The detecting circuit includes a pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor, a source resistor connected between the first power supply and the source electrode of the pMOS transistor and a drain resistor connected to the drain electrode of the pMOS transistor and the second power supply.
摘要翻译：用于检测电源的通电电压的电路包括连接在第一电源和第二电源之间的分压器，第二电源的电位低于第一电源的电位，检测电路连接在第一电源和第二电源之间。分压器包括串联电路，其包括二极管，连接到二极管的第一分压电阻器和连接在第一分压电阻器和第二电源之间的第二分压电阻器。该检测电路包括一个pMOS晶体管，其栅极连接到第一分压电阻和第二分压电阻之间的连接节点，源电阻连接在第一电源和pMOS晶体管的源电极之间，漏电阻连接到 pMOS晶体管的漏电极和第二电源。

7. 发明申请

US20090231903A1 FERROELECTRIC MEMORY AND METHOD FOR TESTING THE SAME 有权
标题翻译：电磁记忆体及其测试方法
公开(公告)号：US20090231903A1
公开(公告)日：2009-09-17
申请号：US12404157
申请日：2009-03-13
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G11C11/22 , G11C11/24 , G11C7/00 , G11C8/08 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C29/50016
摘要： A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the second plate-line voltage to a plate-line voltage.
摘要翻译：在测试模式下，驱动电路和预充电电路将固定电位施加到位线，同时对板线施加第二板线电压。然后，将位线从第一位线预充电电位切换到浮置状态，并且将板线电压从第二板线电压升高到板线电压。

8. 发明申请

US20090108919A1 POWER SUPPLY CIRCUIT USING INSULATED-GATE FIELD-EFFECT TRANSISTORS 有权
标题翻译：使用绝缘栅场效应晶体管的电源电路
公开(公告)号：US20090108919A1
公开(公告)日：2009-04-30
申请号：US12250999
申请日：2008-10-14
申请人： Ryu OGIWARA , Daisaburo Takashima
发明人： Ryu OGIWARA , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A power supply circuit is disclosed. The power supply circuit is provided with a reference voltage generation circuit to receive a voltage from a higher voltage supply so as to generate a reference voltage. The reference voltage from the reference voltage generation circuit is outputted to a power supply voltage generation circuit. The power supply voltage generation circuit boosts the reference voltage to generate a boosted power supply voltage. The boosted power supply voltage is inputted to a bandgap reference circuit. The bandgap reference circuit generates a reference voltage by using the boosted power supply voltage.
摘要翻译：公开了电源电路。电源电路设置有用于接收来自较高电压源的电压以产生参考电压的参考电压产生电路。来自参考电压产生电路的参考电压被输出到电源电压产生电路。电源电压产生电路提升参考电压以产生升高的电源电压。升压的电源电压被输入到带隙基准电路。带隙参考电路通过使用升压电源电压产生参考电压。

9. 发明申请

US20080174290A1 VOLTAGE GENERATION CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20080174290A1
公开(公告)日：2008-07-24
申请号：US11959962
申请日：2007-12-19
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G05F1/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： According to an aspect of the present invention, there is provided a voltage generation circuit including: first and second reference terminals to output first and second reference voltages, respectively; first PMOS and first NMOS transistors connected between high and low level power supply lines in series; an output terminal connected between the first PMOS and first NMOS transistors; a first operational amplifier including: first input terminals each including a gate of a PMOS transistor to be connected to one of the second reference terminal and the output terminal, and a first output terminal connected to the first PMOS transistor; and a second operational amplifier including: second input terminals each including a gate of an NMOS transistor to be connected to one of the first reference terminal and the output terminal, and a second output terminal connected to the first NMOS transistor.
摘要翻译：根据本发明的一个方面，提供了一种电压产生电路，包括：分别输出第一和第二参考电压的第一和第二参考端子; 第一PMOS和第一NMOS晶体管串联在高低电平电源线之间; 连接在第一PMOS和第一NMOS晶体管之间的输出端子; 第一运算放大器，包括：第一输入端，每个包括要连接到第二参考端和输出端之一的PMOS晶体管的栅极;以及连接到第一PMOS晶体管的第一输出端; 以及第二运算放大器，包括：第二输入端子，每个包括要连接到第一参考端子和输出端子之一的NMOS晶体管的栅极，以及连接到第一NMOS晶体管的第二输出端子。

10. 发明申请

US20080116965A1 REFERENCE VOLTAGE GENERATION CIRCUIT 失效
标题翻译：参考电压发生电路
公开(公告)号：US20080116965A1
公开(公告)日：2008-05-22
申请号：US11934970
申请日：2007-11-05
申请人： Ryu OGIWARA , Daisaburo TAKASHIMA
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
IPC分类号： G05F3/02
CPC分类号： G05F3/30
摘要： According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V− node; a first resistor connected between the V− node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V− node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.
摘要翻译：根据本发明的一个方面，提供了一种参考电压产生电路，包括：具有第一栅极，第一源极和第一漏极的第一晶体管; 第二晶体管，具有连接到第一栅极的第二栅极，连接到第一源极和第二漏极的第二源极; 连接在地和V节点之间的第一二极管; 连接在V节点和第一漏极之间的第一电阻器; 连接在地和V +节点之间的第二二极管和第二电阻器; 连接在V +节点和第一漏极之间的第三电阻器; 运算放大器，包括连接到V +节点和V节点的输入端口以及连接到第一门极和第二门极的输出端口; 以及连接在地和第二漏极之间的第四电阻器。

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