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1. 发明授权

US08045358B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08045358B2
公开(公告)日：2011-10-25
申请号：US12635590
申请日：2009-12-10
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having series-connected memory cells; wordlines; and a bitline pair connected to the memory cell blocks, one functioning as a readout bitline, the other one functioning as a reference bitline; an amplification circuit connected to the bitline pair to amplify a signal difference therebetween; and a reference voltage generation circuit including: a dummy memory cell block that has the same configuration as the memory cell block, that has one terminal connected to a first dummy plate line and that has the other terminal connected to the reference bitline; and a paraelectric capacitor that has one terminal connected to a second dummy plate line and that has the other terminal connected to the reference bitline.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：存储单元阵列，包括：具有串联存储单元的存储单元块; 字线以及连接到存储单元块的位线对，一个用作读出位线，另一个用作参考位线; 连接到所述位线对的放大电路，以放大其间的信号差; 以及参考电压产生电路，包括：具有与所述存储单元块相同配置的虚拟存储单元块，其具有连接到第一虚设板线并且具有连接到所述参考位线的另一个端子的一个端子; 以及具有一个端子连接到第二虚拟板线并且另一个端子连接到参考位线的顺电电容器。

2. 发明授权

US07852142B2 Reference voltage generating circuit for use of integrated circuit 有权
标题翻译：用于集成电路的基准电压发生电路
公开(公告)号：US07852142B2
公开(公告)日：2010-12-14
申请号：US12250121
申请日：2008-10-13
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage.
摘要翻译：放大电路接收比较器的输出。输出提供给第一，第二和第三晶体管的每个栅极。第一和第二电阻串联连接。第一和第二电阻器和第一二极管连接到第一晶体管的漏极。第二个二极管并联连接。第二二极管连接到第三电阻器的一端。第三电阻器的另一端连接到第二晶体管的漏极。第四和第五电阻串联连接。第四电阻器的一端连接到第二晶体管的漏极。比较器接收分别从第一和第二电阻器之间的连接节点获得的第一和第二反馈电压以及第四和第五电阻器之间的连接节点。第三晶体管的漏极输出参考电压。

3. 发明申请

US20100090727A1 VOLTAGE DETECTION CIRCUIT AND BGR VOLTAGE DETECTION CIRCUIT 审中-公开
标题翻译：电压检测电路和BGR电压检测电路
公开(公告)号：US20100090727A1
公开(公告)日：2010-04-15
申请号：US12563980
申请日：2009-09-21
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： H03K5/153 , H03K5/00
CPC分类号： H03K17/223 , H03K5/153
摘要： A voltage detection circuit of the present invention includes an NMOS transistor diode-connected, a gate and a drain thereof being supplied with a power supply voltage, a resistor connected between a source of the NMOS transistor and a ground potential, and a source voltage detection circuit receiving a voltage of the source, wherein an NMOS type transistor is employed as the NMOS transistor, a channel width and a channel length of the NMOS type transistor being set in such a manner that an operating point on a VG-ID curve of the NMOS type transistor may come to a certain point, at the certain point, a drain current of the NMOS type transistor being constant even if the temperature fluctuates.
摘要翻译：本发明的电压检测电路包括NMOS晶体管二极管连接，其栅极和漏极被提供有电源电压，连接在NMOS晶体管的源极和接地电位之间的电阻和源电压检测接收源的电压的电路，其中使用NMOS型晶体管作为NMOS晶体管，NMOS晶体管的沟道宽度和沟道长度被设置为使得在所述NMOS晶体管的VG-ID曲线上的工作点 NMOS型晶体管可以到达某一点，在某一点，即使温度波动，NMOS型晶体管的漏极电流恒定。

4. 发明授权

US07679412B2 Power supply circuit 失效
标题翻译：电源电路
公开(公告)号：US07679412B2
公开(公告)日：2010-03-16
申请号：US12239188
申请日：2008-09-26
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： H03L7/00
CPC分类号： G11C5/143 , G11C5/147
摘要： According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal.
摘要翻译：根据本发明的一个方面，提供一种电源电路，包括：检测电路，其连接到外部电源电压，并且输出指示外部电源电压是否处于丢弃状态的第一信号外部电源电压降低到参考电压以下; 控制电路，包括：延迟电路，其输出通过将所述第一信号延迟参考时间获取的第二信号; 以及确定电路，其基于所述第一信号和所述第二信号输出第三信号; 生成电路，其从所述外部电源电压产生内部电源电压，并且提供所述内部电源电压; 以及中断电路，其基于所述第三信号中断从所述发电电路提供的内部电源电压。

5. 发明授权

US07589513B2 Reference voltage generator circuit 有权
标题翻译：参考电压发生器电路
公开(公告)号：US07589513B2
公开(公告)日：2009-09-15
申请号：US11783039
申请日：2007-04-05
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , G11C5/147 , G11C7/04
摘要： A reference voltage generator circuit comprises a first current path and a second current path. The first current path is formed between an input terminal supplied with a first reference voltage and an output terminal and including a first diode and a first resistor serially connected from the input terminal. The second current path is formed between the input terminal and the output terminal and including a second diode, a second resistor and a third resistor serially connected from the input terminal. A comparator is supplied with a voltage on a node between the first diode and the first resistor and a voltage on a node between the second resistor and the third resistor for comparative amplification. A transistor is connected between the output terminal and a second reference voltage and having a control terminal to receive an output from the first comparator.
摘要翻译：参考电压发生器电路包括第一电流路径和第二电流路径。第一电流路径形成在提供有第一参考电压的输入端子和输出端子之间，并且包括第一二极管和从输入端子串联连接的第一电阻器。第二电流路径形成在输入端子和输出端子之间，并且包括从输入端子串联连接的第二二极管，第二电阻器和第三电阻器。比较器在第一二极管和第一电阻之间的节点上提供电压，并且在第二电阻器和第三电阻器之间的节点上的电压用于比较放大。晶体管连接在输出端和第二参考电压之间，并且具有用于接收来自第一比较器的输出的控制端。

6. 发明授权

US07583114B2 Supply voltage sensing circuit 失效
标题翻译：电源电压检测电路
公开(公告)号：US07583114B2
公开(公告)日：2009-09-01
申请号：US11684214
申请日：2007-03-09
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： H03L7/00
CPC分类号： G01R19/16552 , G01R19/16519 , G11C5/147
摘要： A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.
摘要翻译：电源电压检测电路包括内部电源电路，其提供恒定的输出电压，而不管电源电压如何。延迟电路通过延迟输出电压的变化来产生延迟信号。分压电路通过以一定的分频比除电源电压来产生分压。 p型MOS晶体管具有给定延迟信号的源极和给定分压的栅极，并且当电源电压降低到一定值以下时导通。输出电路基于p型MOS晶体管上的漏极电压提供输出电压。

7. 发明授权

US07443709B2 Temperature sensing circuit, voltage generation circuit, and semiconductor storage device 失效
标题翻译：温度检测电路，电压产生电路和半导体存储装置
公开(公告)号：US07443709B2
公开(公告)日：2008-10-28
申请号：US11599363
申请日：2006-11-15
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C29/02 , G11C5/147 , G11C7/04 , G11C7/062 , G11C7/14 , G11C11/22 , G11C29/026 , G11C29/028 , G11C2029/5002 , G11C2207/065
摘要： A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first and second bit lines. A sense amplifier supply voltage generation circuit supplies the sense amplifier with a sense amplifier supply voltage to be used in the comparison and amplification by the sense amplifier. The sense amplifier supply voltage is supplied to a reference potential generation circuit. When data is read out from the memory cell to the first bit line, the reference potential generation circuit supplies, to the second bit line via the dummy cell, a reference potential which fluctuates with a positive correlation to the fluctuation in sense amplifier supply voltage.
摘要翻译：第一位线连接到存储器单元。第二位线连接到具有虚拟电容器的虚拟单元，并且提供与第一位线的电位互补的电位。读出放大器比较和放大第一和第二位线。读出放大器电源电压产生电路为读出放大器提供读出放大器电源电压，以便由读出放大器进行比较和放大。读出放大器电源电压被提供给参考电位产生电路。当数据从存储单元读出到第一位线时，参考电位产生电路经由虚拟单元向第二位线提供与读出放大器电源电压的波动成正相关的波动的基准电位。

8. 发明授权

US07233536B2 Semiconductor memory device having memory cells to store cell data and reference data 失效
标题翻译：具有存储单元数据和参考数据的半导体存储器件
公开(公告)号：US07233536B2
公开(公告)日：2007-06-19
申请号：US11239219
申请日：2005-09-30
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes a memory cell array, a sense amplifier, and a voltage generator. The memory cell array has a plurality of memory cells. Each of the memory cells is written with “0” or “1” as reference data after “0” or “1” as cell data has been read out from the memory cell. The sense amplifier compares and amplifies the reference data and the cell data read from a memory cell. The voltage generator keeps constant rate of change with time of at least one potential supplied for a read operation for the time interval from readout of the cell data is started until completion of readout of the reference data.
摘要翻译：半导体存储器件包括存储单元阵列，读出放大器和电压发生器。存储单元阵列具有多个存储单元。在从存储单元读出单元数据的情况下，每个存储单元都以“0”或“1”作为参考数据写入“0”或“1”之后。读出放大器比较和放大从存储器单元读取的参考数据和单元数据。电压发生器在从开始单元数据的读出开始直至完成读出参考数据的时间间隔内，为读操作提供至少一个电位的时间保持恒定的变化率。

9. 发明申请

US20060067138A1 Semiconductor memory device having memory cells to store cell data and reference data 失效
标题翻译：具有存储单元数据和参考数据的半导体存储器件
公开(公告)号：US20060067138A1
公开(公告)日：2006-03-30
申请号：US11239219
申请日：2005-09-30
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C16/04
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes a memory cell array, a sense amplifier, and a voltage generator. The memory cell array has a plurality of memory cells. Each of the memory cells is written with “0” or “1” as reference data after “0” or “1” as cell data has been read out from the memory cell. The sense amplifier compares and amplifies the reference data and the cell data read from a memory cell. The voltage generator keeps constant rate of change with time of at least one potential supplied for a read operation for the time interval from readout of the cell data is started until completion of readout of the reference data.
摘要翻译：半导体存储器件包括存储单元阵列，读出放大器和电压发生器。存储单元阵列具有多个存储单元。在从存储单元读出单元数据的情况下，每个存储单元都以“0”或“1”作为参考数据写入“0”或“1”之后。读出放大器比较和放大从存储器单元读取的参考数据和单元数据。电压发生器在从开始单元数据的读出开始直至完成读出参考数据的时间间隔内，为读操作提供至少一个电位的时间保持恒定的变化率。

10. 发明授权

US06993691B2 Series connected TC unit type ferroelectric RAM and test method thereof 失效
公开(公告)号：US06993691B2
公开(公告)日：2006-01-31
申请号：US10120146
申请日：2002-04-11
申请人： Ryu Ogiwara , Daisaburo Takashima , Yukihito Oowaki , Katsuhiko Hoya , Takeshi Watanabe
发明人： Ryu Ogiwara , Daisaburo Takashima , Yukihito Oowaki , Katsuhiko Hoya , Takeshi Watanabe
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/22
摘要： Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

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