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71. 发明授权

US07073961B2 Optical sub-assembly packaging techniques that incorporate optical lenses 有权
标题翻译：包含光学透镜的光学子组件封装技术
公开(公告)号：US07073961B2
公开(公告)日：2006-07-11
申请号：US11050073
申请日：2005-02-01
申请人： William Paul Mazotti , Jia Liu , Luu Thanh Nguyen , Haryanto Chandra , Peter Deane , Todd Thyes , Brian Huss , John Rukavina , Glenn Woodhouse
发明人： William Paul Mazotti , Jia Liu , Luu Thanh Nguyen , Haryanto Chandra , Peter Deane , Todd Thyes , Brian Huss , John Rukavina , Glenn Woodhouse
IPC分类号： G02B6/36
CPC分类号： G02B6/4292 , G02B6/4201 , G02B6/4204 , G02B6/4231 , G02B6/4239 , G02B6/4249 , G02B6/4251
摘要： Techniques for manufacturing an optical transmission device in a manner so that the photonic device is protected from damage that can be caused by exposure to the environment and physical handling are described. The invention involves placing a lens or a lens array over a photonic device, either with or without the use of a receptacle device, such that the photonic device is contained within a sealed cavity. The invention has three main embodiments in which the photonic device can be hermetically sealed, quasi-hermetically sealed, or non-hermetically sealed. The optical transmission device can be configured to serve as an optical receiver, detector, or a transceiver device.
摘要翻译：描述了以使得光子器件免受可能由于暴露于环境和物理处理引起的损害的方式制造光传输装置的技术。本发明涉及将透镜或透镜阵列放置在光子器件上，无论是否使用插座器件，使得光子器件被包含在密封腔内。本发明具有三个主要实施例，其中光子器件可被气密密封，准气密密封或非气密密封。光传输设备可以被配置为用作光接收器，检测器或收发器设备。

72. 发明授权

US07073177B2 Resource managing system for changing resource consumption state of the lower priority resource entity to more restrictive state when resource reached critical level 有权
标题翻译：资源管理系统，当资源达到关键水平时，将较低优先级资源实体的资源消耗状态更改为更严格的状态
公开(公告)号：US07073177B2
公开(公告)日：2006-07-04
申请号：US10045514
申请日：2001-10-26
申请人： William F. Foote , Hideya Kawahara
发明人： William F. Foote , Hideya Kawahara
IPC分类号： G06F9/46
CPC分类号： G06F11/28 , G06F9/50
摘要： Disclosed are methods and apparatus for managing resources. In general terms, a resource manager manages resource consumption of several resource entities which are each capable of consuming resources. The resource manager tracks the availability of such resources and determines whether a resource is critically short or reaches a particular usage level. When a resource becomes critically short or reaches a particular usage level, the resource manager selects one or more resource entities based on one or more criteria. For example, a resource entity which has the least restrictive resource usage policy or state is selected. The resource manager then requests that the selected resource entity changes its resource usage state to a more restrictive state. Of course, when resource usage reaches an acceptable level, the resource manager may also inform each resource entity (or previously selected resource entities) that they may set their resource consumption state to a less restrictive state.
摘要翻译：公开了用于管理资源的方法和装置。一般来说，资源管理器管理能够消耗资源的几个资源实体的资源消耗。资源管理器跟踪这种资源的可用性，并确定资源是否严重短暂或达到特定的使用级别。当资源变得严重短暂或达到特定使用水平时，资源管理器基于一个或多个标准来选择一个或多个资源实体。例如，选择具有最少限制性资源使用策略或状态的资源实体。资源管理器然后请求所选择的资源实体将其资源使用状态改变到更严格的状态。当然，当资源使用达到可接受的水平时，资源管理器也可以通知每个资源实体（或先前选择的资源实体），他们可以将它们的资源消耗状态设置为较少的限制状态。

73. 发明授权

US07072786B2 Inspection system setup techniques 有权
标题翻译：检测系统设置技术
公开(公告)号：US07072786B2
公开(公告)日：2006-07-04
申请号：US11238357
申请日：2005-09-28
申请人： David Bruce Coldren , Prashant A. Aji , David Winslow Randall , Sharon Marie McCauley
发明人： David Bruce Coldren , Prashant A. Aji , David Winslow Randall , Sharon Marie McCauley
IPC分类号： G06F19/00 , G06K9/00
CPC分类号： G05B19/41875 , G05B2219/32197 , G05B2219/45031 , H01L21/67276 , Y02P90/20 , Y02P90/22
摘要： Techniques for efficiently setting up inspection, metrology, and review systems for operating upon semiconductor wafers are described. Specifically, this involves setting up recipes that allows each system to accurately inspect semiconductor wafers. The invention gathers pertinent information from these tools and presents the information to users in a way that greatly reduces the time required to complete a recipe. One system embodiment includes an inspection system and a review station that is communicatively linked such that the review station can read from and write to an entire set of data stored at the inspection system. The set of data includes image files of features detected by the inspection system.
摘要翻译：描述了用于有效地设置用于在半导体晶片上操作的检查，计量和审查系统的技术。具体来说，这涉及设置允许每个系统准确检查半导体晶片的配方。本发明从这些工具收集相关信息，并以大大减少完成配方所需时间的方式向用户提供信息。一个系统实施例包括检查系统和通信链接的检查站，使得检查站可以读取和写入存储在检查系统中的整个数据集合。该组数据包括由检查系统检测到的特征的图像文件。

74. 发明授权

US07067927B1 Die with integral pedestal having insulated walls 有权
标题翻译：具有绝缘壁的整体基座的模具
公开(公告)号：US07067927B1
公开(公告)日：2006-06-27
申请号：US11048182
申请日：2005-01-31
申请人： Shahram Mostafazadeh
发明人： Shahram Mostafazadeh
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/0657 , H01L23/3107 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L2224/274 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/10155 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A variety of techniques and structures are described that integrate an insulated pedestal into the back surface of integrated circuit dice. The die has an insulated integral pedestal formed therein that acts as a spacer. The pedestal has a footprint that is smaller than the total footprint of the die so that a portion of the active region of the die overhangs the pedestal. The geometry of the pedestal may be widely varied and in some embodiments, multiple pedestals may be provided on the stacked die. In another aspect, the pedestals are formed at the wafer level such that the pedestals are defined in the back surface of the wafer. Often, the thickness of the pedestals will be thicker than the portions of the wafer outside the pedestal areas. The described dice are particularly well suited for use in stacked die packages.
摘要翻译：描述了将绝缘基座集成到集成电路芯片的背面中的各种技术和结构。模具具有形成在其中的隔离的一体式基座，其作为间隔件。基座具有小于模具的总占地面积的足迹，使得模具的有源区域的一部分悬垂在基座上。基座的几何形状可以是广泛变化的，并且在一些实施例中，可以在堆叠的模具上设置多个基座。在另一方面，基座形成在晶片级，使得基座被限定在晶片的后表面中。通常，基座的厚度将比基座区域外的晶片的部分厚。所描述的骰子特别适用于堆叠的模具包装。

75. 发明授权

US07067354B2 Electrical die contact structure and fabrication method 有权
公开(公告)号：US07067354B2
公开(公告)日：2006-06-27
申请号：US10871337
申请日：2004-06-18
申请人： Ashok Prabhu
发明人： Ashok Prabhu
IPC分类号： H01L21/44
CPC分类号： H01L27/14618 , H01L23/482 , H01L23/4827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. The second surface of the semiconductor substrate includes a multiplicity of backside electrical connectors that are in overlapping electrical contact with corresponding electrical contact pad extensions forming lap joint electrical connections between the backside electrical connectors and the corresponding electrical contact pad extensions. Methods for constructing such devices and connections are also disclosed.

76. 发明授权

US07064472B2 Electroactive polymer devices for moving fluid 有权
标题翻译：用于移动流体的电动聚合物装置
公开(公告)号：US07064472B2
公开(公告)日：2006-06-20
申请号：US10393506
申请日：2003-03-18
申请人： Ronald E. Pelrine , Roy David Kornbluh , Scott E. Stanford , Qibing Pei , Richard Heydt , Joseph S. Eckerle , Jonathan R. Heim
发明人： Ronald E. Pelrine , Roy David Kornbluh , Scott E. Stanford , Qibing Pei , Richard Heydt , Joseph S. Eckerle , Jonathan R. Heim
IPC分类号： F04B45/02 , H01L41/08
CPC分类号： A61M5/142 , A61M5/14212 , A61M5/14216 , A61M5/14224 , A61M5/14236 , A61M5/14276 , A61M2205/0283 , A63H3/365 , B60G2400/60 , B60G2401/11 , B60G2401/23 , B60G2500/20 , F01L2101/00 , F02G1/043 , F02G2243/52 , F04B17/00 , F04B35/00 , F04B35/04 , F04B35/045 , F04B43/04 , F04B43/043 , F04B43/08 , F04B43/084 , F04B43/09 , F04B43/095 , F04D33/00 , F05C2225/08 , F15C5/00 , F16F15/005 , F25B9/14 , H02N11/006 , H04R19/02 , H04R23/00 , Y10S310/80
摘要： The invention describes devices for performing thermodynamic work on a fluid, such as pumps, compressors and fans. The thermodynamic work may be used to provide a driving force for moving the fluid. Work performed on the fluid may be transmitted to other devices, such as a piston in a hydraulic actuation device. The devices may include one or more electroactive polymer transducers with an electroactive polymer that deflects in response to an application of an electric field. The electroactive polymer may be in contact with a fluid where the deflection of the electroactive polymer may be used to perform thermodynamic work on the fluid. The devices may be designed to efficiently operate at a plurality of operating conditions, such as operating conditions that produce an acoustic signal above or below the human hearing range. The devices may be used in thermal control systems, such as refrigeration system, cooling systems and heating systems.
摘要翻译：本发明描述了用于对诸如泵，压缩机和风扇等流体进行热力学工作的装置。热力学工作可用于提供用于移动流体的驱动力。在流体上进行的工作可以传送到其它装置，例如液压致动装置中的活塞。装置可以包括一个或多个电活性聚合物换能器，其具有响应于电场施加而偏转的电活性聚合物。电活性聚合物可以与流体接触，其中电活性聚合物的偏转可用于对流体进行热力学作用。这些装置可被设计成在诸如在人类听觉范围之上或之下产生声学信号的操作条件的多个操作条件下有效地操作。这些装置可用于热控制系统，例如制冷系统，冷却系统和加热系统。

77. 发明授权

US07064419B1 Die attach region for use in a micro-array integrated circuit package 有权
标题翻译：芯片附着区域用于微阵列集成电路封装
公开(公告)号：US07064419B1
公开(公告)日：2006-06-20
申请号：US10871320
申请日：2004-06-18
申请人： Jaime A. Bayan , Ashok S. Prabhu , Chan Chee Ling , Lye Meng Kong , Santhiran S O Nadarajah
发明人： Jaime A. Bayan , Ashok S. Prabhu , Chan Chee Ling , Lye Meng Kong , Santhiran S O Nadarajah
IPC分类号： H01L23/495
CPC分类号： H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10T428/24843 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.
摘要翻译：描述了用于IC封装的管芯附着区域。管芯附接区域采用与多个支撑立管互连的多个柱，以提供支撑半导体管芯的结构，同时便于在封装期间在管芯下方的密封剂材料的流动。柱和立管可以布置成多个构造，每个构造都促进密封材料的流动。为了便于制造和效率，该管芯附着区域可以结合到引线框架结构或基板面板中。

78. 发明授权

US07063617B2 Wins of restricted credits in a gaming machine 有权
公开(公告)号：US07063617B2
公开(公告)日：2006-06-20
申请号：US10082911
申请日：2002-02-25
申请人： William R. Brosnan , Bryan D. Wolf , Steven G. LeMay
发明人： William R. Brosnan , Bryan D. Wolf , Steven G. LeMay
IPC分类号： A63F13/00
CPC分类号： G07F17/32 , G06Q30/0207 , G06Q30/0209 , G07F17/323 , G07F17/3244
摘要： Disclosed is a gaming system and method designed or configured to provide wins of restricted credits. Restricted credits may be awarded according to the same or a different pay table than cashable credits on the same machine or at the same gaming property. Where separate pay tables are used for restricted and cashable credits, the invention may be implemented with a machine that accepts and pays only restricted credit according to a single, fixed internal payout schedule (“pay table”). Alternatively, the invention may be implemented with a machine that pays restricted credit according to one fixed internal pay table and cashable credit according to another fixed internal pay table. Or, a machine may pay restricted credit according to an external pay table provided by a host system to which the machine is connected.

79. 发明授权

US07061598B1 Darkfield inspection system having photodetector array 有权
标题翻译：具有光电检测器阵列的暗场检查系统
公开(公告)号：US07061598B1
公开(公告)日：2006-06-13
申请号：US10315340
申请日：2002-12-09
申请人： Christopher F. Bevis , David W. Shortt
发明人： Christopher F. Bevis , David W. Shortt
IPC分类号： G01N21/00
CPC分类号： G01N21/47 , G01N21/9501 , G01N2021/8822
摘要： A darkfield surface inspection tool of the invention includes an illumination source for illuminating a workpiece and generating a light scattering pattern. The light scattering pattern being configured such that the positions of the light beams of the scattering pattern are uniquely related to the scattering angles of the light beams as they are scattered from the workpiece. The tool also includes a photodetector array positioned at a detector surface to detect the light scattering pattern as it reaches the detector surface. The photodetector array produces an electrical signal that is received by signal processing electronics of the tool and can be used to characterize defects on the workpiece. The invention also includes darkfield surface inspection methods.
摘要翻译：本发明的暗视场表面检查工具包括用于照亮工件并产生光散射图案的照明源。光散射图案被配置为使得散射图案的光束的位置与从工件散射的光束的散射角唯一相关。该工具还包括位于检测器表面处的光电检测器阵列，以便在其到达检测器表面时检测光散射图案。光电检测器阵列产生由工具的信号处理电路接收的电信号，并且可用于表征工件上的缺陷。本发明还包括暗场表面检查方法。

80. 发明授权

US07059940B2 Jet singulation 失效
公开(公告)号：US07059940B2
公开(公告)日：2006-06-13
申请号：US10661385
申请日：2003-09-12
申请人： Seill Seo , Steven Tay , Shan Jiang
发明人： Seill Seo , Steven Tay , Shan Jiang
IPC分类号： B24B1/00
CPC分类号： H01L21/67092 , B24C1/045 , B24C7/0007 , B24C9/006 , H01L21/3043 , H01L21/4803 , H01L21/78 , H05K3/0052 , Y02P70/179 , Y10T117/10
摘要： Techniques for singulating a substrate into a plurality of component parts is disclosed. The singulation techniques include generating a jet stream in order to cut through large components so as to produce smaller components. The techniques are particularly suitable for singulating surface mount devices such as chip scale packages, ball grid arrays (BGA), flip chips, lead less packages (QFN) and the like. The techniques are also suitable for singulating photonic devices.

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