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    • 64. 发明授权
    • Recording apparatus
    • 记录装置
    • US06693728B1
    • 2004-02-17
    • US09562140
    • 2000-05-01
    • Hiroyuki KinoshitaTakao Nakamura
    • Hiroyuki KinoshitaTakao Nakamura
    • H04N121
    • H04N1/00519H04N2201/0094
    • The present invention relates to a recording apparatus provided with recording device for effecting recording on a sheet which has sheet containing device provided detachably attachably to a main body of the apparatus, sheet supporting device disposed in the sheet containing device, for supporting the sheet, lift device for lifting the sheet supporting device from the sheet containing device in operative association with an operation of attaching the sheet containing device to the main body of the apparatus, and sheet feeding device for feeding the sheet from the sheet feeding device for feeding the sheet from the sheet supporting device lifted by the lift device toward the recording device.
    • 本发明涉及一种具有记录装置的记录装置,该记录装置用于对片材进行记录,该片材具有可装卸地安装在该装置的主体上的片材容纳装置,设置在片材容纳装置中的片材支撑装置,用于支撑片材,提升装置 用于从片材容纳装置提升片材支撑装置的装置,其与将片材容纳装置附接到装置的主体的操作有关;以及片材进给装置,用于从片材进给装置供给片材,以将片材从 所述片材支撑装置由提升装置朝向记录装置提升。
    • 68. 发明授权
    • Variable length code decoder using a content addressable memory with
match inhibiting gate
    • 使用具有匹配禁止门的内容可寻址存储器的可变长度码解码器
    • US5642114A
    • 1997-06-24
    • US351253
    • 1995-01-24
    • Eiji KomotoTakao Nakamura
    • Eiji KomotoTakao Nakamura
    • G11C11/00G11C15/00G11C15/04H03M7/42H03M7/40
    • H03M7/425G11C11/005G11C15/00G11C15/04
    • The present invention relates to a variable-length code decoding circuit for decoding an input variable-length code string and a variable-length code decoding system using the same. A typical variable-length code decoding circuit of the present invention includes a CAM cell 10 for storing a variable-length code bit and a RAM cell 20 which is paired with the CAM cell 10 for storing a mask bit so as to perform a masking operation. The variable-length code decoding circuit further includes an NMOS transistor 30 which is coupled between the CAM cell 10 and a match line ML for selectively disconnecting the CAM cell 10 from the match line ML in response to an output of the RAM cell 20. The CAM cell 10 collates a bit of the input variables-length code string with the stored code bit. When the input bit matches the stored code bit, the CAM cell 10 outputs an H level matching to the match line ML and otherwise it outputs an L level unmatching to the match line ML. If the CAM cell 10 does not relate to the collating operation that is, if it does not matter whether there is a match, the RAM cell 20 corresponding to the CAM cell 10 outputs an L level signal to turn off the NMOS transistor 30. When the NMOS 30 is turned off, the output of the CAM cell 10 is not transmitted to the match line ML.
    • PCT No.PCT / JP94 / 00646 Sec。 371日期1995年1月24日 102(e)1995年1月24日PCT PCT 1994年4月19日PCT公布。 第WO94 / 24672号公报 日期:1994年10月27日本发明涉及用于解码输入可变长度代码串的可变长度码解码电路和使用其的可变长度码解码系统。 本发明的典型的可变长度码解码电路包括用于存储可变长度码位的CAM单元10和与用于存储掩码位的CAM单元10配对以便执行掩蔽操作的RAM单元20 。 可变长度码解码电路还包括NMOS晶体管30,其耦合在CAM单元10和匹配线ML之间,用于响应于RAM单元20的输出选择性地将CAM单元10与匹配线ML断开。 CAM单元10将输入变量长度代码串的位与存储的代码位进行核对。 当输入位与存储的代码位匹配时,CAM单元10输出与匹配线ML匹配的H电平,否则将其输出到匹配线ML的L电平不匹配。 如果CAM单元10与对照操作无关,则如果不存在匹配,则与CAM单元10相对应的RAM单元20输​​出L电平信号以关闭NMOS晶体管30.当 NMOS30截止,CAM单元10的输出不发送到匹配线ML。