专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US08637958B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

62. 发明授权

US08575670B2 Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate 有权
标题翻译：在非常薄的半导体绝缘体（ETSOI）衬底上形成的嵌入式动态随机存取存储器件
公开(公告)号：US08575670B2
公开(公告)日：2013-11-05
申请号：US13316056
申请日：2011-12-09
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10861 , H01L28/91 , H01L29/945
摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
摘要翻译：一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。电容器存在于沟槽的下部。电介质垫片存在于沟槽上部的侧壁上。介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。导电材料填充物存在于沟槽的上部。半导体器件存在于与沟槽相邻的SOI层上。半导体器件通过导电材料填充与电容器电连通。

63. 发明授权

US08536649B2 Method to reduce threshold voltage variability with through gate well implant 失效
标题翻译：通过栅极井注入降低阈值电压变化的方法
公开(公告)号：US08536649B2
公开(公告)日：2013-09-17
申请号：US13608860
申请日：2012-09-10
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译：本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。存在于半导体层的沟道部分上的栅极结构。第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

64. 发明授权

US08507915B2 Low resistance embedded strap for a trench capacitor 有权
公开(公告)号：US08507915B2
公开(公告)日：2013-08-13
申请号：US13307787
申请日：2011-11-30
申请人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L29/94
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

65. 发明申请

US20130032868A1 TRENCH CAPACITOR WITH SPACER-LESS FABRICATION PROCESS 失效
标题翻译：具有无间隙制造工艺的TRENCH电容器
公开(公告)号：US20130032868A1
公开(公告)日：2013-02-07
申请号：US13198100
申请日：2011-08-04
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/0692 , H01L21/3081 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.
摘要翻译：公开了一种沟槽电容器和制造方法。掺杂SOI区域使得用于沟槽加宽的选择性各向同性蚀刻不会导致SOI区域的明显的回退，并且在沟槽的上部不需要间隔物。

66. 发明授权

US08354675B2 Enhanced capacitance deep trench capacitor for EDRAM 有权
标题翻译： EDRAM增强型电容深沟槽电容器
公开(公告)号：US08354675B2
公开(公告)日：2013-01-15
申请号：US12775532
申请日：2010-05-07
申请人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
发明人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

67. 发明授权

US08242549B2 Dynamic random access memory cell including an asymmetric transistor and a columnar capacitor 有权
标题翻译：包括非对称晶体管和柱状电容器的动态随机存取存储器单元
公开(公告)号：US08242549B2
公开(公告)日：2012-08-14
申请号：US12700807
申请日：2010-02-05
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Chengwen Pei , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L21/823431 , H01L27/10823 , H01L27/1085 , H01L27/10876 , H01L27/10879 , H01L28/60 , H01L29/66795 , H01L29/785
摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.
摘要翻译：在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。掺杂半导体柱构成电容器的内部电极。在半导体鳍片和半导体柱上形成介电层和导电材料层。图案化导电材料层以形成用于电容器的外部电极和栅电极。可以进行单侧晕圈植入。源极和漏极区域形成在半导体鳍片中以形成存取晶体管。源极区域电连接到电容器的内部电极。存取晶体管和电容器共同构成DRAM单元。

68. 发明申请

US20110152444A1 NETWORK COPOLYMER CROSSLINKED COMPOSITIONS AND METHODS OF MAKING THE SAME 有权
标题翻译：网络共聚物交联组合物及其制备方法
公开(公告)号：US20110152444A1
公开(公告)日：2011-06-23
申请号：US12646333
申请日：2009-12-23
申请人： Ning LU , Sigfredo Gonzalez , Emie M. Silvestre , Geng Wang
发明人： Ning LU , Sigfredo Gonzalez , Emie M. Silvestre , Geng Wang
IPC分类号： C08L41/00 , C08F230/02 , C08F228/02 , C08L43/00
CPC分类号： C08F220/38 , C08F228/02 , C08F230/02
摘要： The present invention is directed to a network composition having the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2═C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r where R3═H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100; c is 0 to about 100; d is 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and CH2═C(R3)C(O)OXa′(C2H4O)b′(C3H6O)c′(C4H8O)d′—SO3—Y) where R3═H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a′ is 0 to about 100; b′ is 0 to about 100; c′ is 0 to about 100; d′ is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).
摘要翻译：本发明涉及一种具有以下反应产物的网络组合物：（i）至少一种选自[CH 2 = C（R 3）C（O）O X a（C 2 H 4 O））的阴离子可聚合烯属不饱和单体（I） b（C 3 H 6 O）c（C 4 H 8 O）d] pP（O）（OY）q（OZ）r其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0〜100; b为0至约100; c为0至约100; d为0至约100; q为0〜2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; （C 3 H 6 O）c'（C 4 H 8 O）d-SO 3-Y）其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0至约100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

69. 发明申请

US20110152423A1 NETWORK COPOLYMER CROSSLINKED EMULSIONS AND DEMULSIFYING COMPOSITIONS COMPRISING THE SAME 有权
标题翻译：网络共聚物交联乳液和包含它们的组合物
公开(公告)号：US20110152423A1
公开(公告)日：2011-06-23
申请号：US12646364
申请日：2009-12-23
申请人： Ning Lu , Sigfredo Gonzalez , Emie M. Silvestre , Geng Wang
发明人： Ning Lu , Sigfredo Gonzalez , Emie M. Silvestre , Geng Wang
IPC分类号： C08K5/541 , C08L43/02
CPC分类号： C08F220/26 , A61K8/8152 , A61K2800/54 , A61Q1/02 , A61Q5/12 , C08F220/38 , C08F230/02
摘要： The present invention is directed to a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2═C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r where R3═H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100;c is 0 to about 100; d is 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and CH2═C(R3)C(O)OXa′(C2H4O)b′(C3H6O)c′(C4H8O)d′—SO3—Y) where R3═H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a′ is 0 to about 100; b′ is 0 to about 100; c′ is 0 to about 100; d′ is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).
摘要翻译：本发明涉及一种网络组合物，其反应产物为：（i）至少一种选自[CH 2 = C（R 3）C（O）O X a（C 2 H 4 O）b的阴离子可聚合烯属不饱和单体（I）（C 3 H 6 O）c（C 4 H 8 O）d] pP（O）（OY）q（OZ）r其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0〜100; b为0至约100; c为0至约100; d为0至约100; q为0〜2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; （C 3 H 6 O）c'（C 4 H 8 O）d-SO 3-Y）其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0至约100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

70. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式