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61. 发明授权

US07449747B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07449747B2
公开(公告)日：2008-11-11
申请号：US11311162
申请日：2005-12-20
申请人： Tomoyuki Ishii , Kazunori Furusawa , Hideaki Kurata , Yoshihiro Ikeda
发明人： Tomoyuki Ishii , Kazunori Furusawa , Hideaki Kurata , Yoshihiro Ikeda
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , B82Y10/00 , G11C11/5621 , G11C16/0458 , G11C2211/5612 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/7887
摘要： Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.
摘要翻译：闪存正在迅速降价。需要一种允许大小缩小并适合多值内存的新内存系统。如果使用反转层作为布线，则可以使适用于具有多级阈值的多值存储器的AND型闪速存储器的面积小; 然而，它具有从细胞到细胞的书写特征大大变化的缺点。实现多值存储器的另一个有希望的方法是改变存储位置。然而，这种方法在操作时存在干扰问题。本发明提供了实现具有减小的写入特性的单元到单元变化的半导体存储器件的一种方式。半导体存储器具有彼此平行形成的源极区域和漏极区域以及辅助电极，其在源极和漏极区域之间并且平行于其而不重叠，从而在写入时使用辅助电极辅助电极作为用于在源极侧注入的热电子的辅助电极，并且在读取时使用形成在辅助电极下方的反型层作为源极区域或漏极区域。

62. 发明申请

US20060039230A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060039230A1
公开(公告)日：2006-02-23
申请号：US11180659
申请日：2005-07-14
申请人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
发明人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
IPC分类号： G11C8/02
CPC分类号： G11C8/14
摘要： An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.
摘要翻译：本发明的目的是提供一种半导体存储器件，其能够防止由于字线的下降引起的缺陷以及由于在存储器块的端部处的字线的间距的干扰而导致的图案精度的劣化。多个虚拟字线设置在存储器块的末端，为虚拟字线安装字驱动器以控制形成在虚拟字线下面的虚拟存储器单元的阈值电压。此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现高产率和可靠的操作。

63. 发明申请

US20060023515A1 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20060023515A1
公开(公告)日：2006-02-02
申请号：US11189977
申请日：2005-07-27
申请人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
发明人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
IPC分类号： G11C7/10
CPC分类号： G11C16/0491 , G11C16/0425 , G11C16/0458 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
摘要翻译：非易失性存储器包括各自具有依次重复串联连接的第一控制晶体管，存储晶体管，第二控制晶体管和存储器晶体管的电路。在控制晶体管导通时，在与串行方向相交的方向上形成反转层。选择电路选择放置在第一控制晶体管下方的反相层及其对应的读/写电路的连接。放置在与存储晶体管相邻的两侧的控制晶体管被导通以执行读取。放置在从一侧到另一侧观察的第二控制晶体管的两侧上的第一控制晶体管被导通，以通过右和左存储晶体管中的一个来执行向左和右存储晶体管中的另一个的写入。选择电路以这样的方式连接读/写电路和反转层，即在相同存储晶体管的读和写中使用相同的读/写电路。

64. 发明申请

US20060007737A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060007737A1
公开(公告)日：2006-01-12
申请号：US11224964
申请日：2005-09-14
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

65. 发明授权

US06930924B2 Nonvolatile memory and method of programming the same memory 有权
标题翻译：非易失性存储器和编程相同存储器的方法
公开(公告)号：US06930924B2
公开(公告)日：2005-08-16
申请号：US10404101
申请日：2003-04-02
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
摘要翻译：提供了一种编程非易失性存储器的方法，其可以解决现有闪存的数据写入系统的问题，即位线的负载电容变大，位线达到预定电位所需的时间变为因此，数据写入操作所需的时间变得更长，并且由于存储器阵列的存储器电容越多，存储器阵列的长度越长，位线的数量越多，位线的数量越多，因此功耗也变大。在本发明的非易失性存储器中，包括其中多个存储器单元并联连接在局部位线和局部漏极线之间的AND型存储器阵列，通过向局部漏极线提供相对较高的电压来预充电，公共漏极线侧（主位线的相对侧），主位线通过向其施加0V的电压或根据写入数据的相对较小的电压来选择性地预充电，此后，漏极电流仅施加到所选择的通过将写入电压施加到字线来写入数据的存储器单元，以便将热电子注入浮动栅极。

66. 发明申请

US20050029681A1 Semiconductor memory device and method for producing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050029681A1
公开(公告)日：2005-02-10
申请号：US10883738
申请日：2004-07-06
申请人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
发明人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
IPC分类号： G11C8/00 , G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5621 , G11C11/5671 , G11C16/0433 , G11C16/0458 , G11C16/0475 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521
摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.
摘要翻译：公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。多个辅助栅极通过栅极氧化膜形成在p型阱的上部。在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。

67. 发明授权

US06521671B1 Micelle dispersion and method for preparation thereof 失效
标题翻译：胶束分散体及其制备方法
公开(公告)号：US06521671B1
公开(公告)日：2003-02-18
申请号：US09673663
申请日：2000-11-06
申请人： Motoharu Ishikawa , Hideaki Kurata
发明人： Motoharu Ishikawa , Hideaki Kurata
IPC分类号： B01F1700
CPC分类号： C25D15/00 , G02B5/201 , G02B5/223
摘要： A micelle dispersion containing hydrophobic particles, conductive particles and a surfactant of a ferrocene derivative dispersed in an aqueous medium. The surfactant of a ferrocene derivative in an equilibrium concentration contains an oxidized compound in a concentration of 40 &mgr;g/ml or less and a reduced compound in a concentration of 50 to 300 &mgr;g/ml. A process for producing a micelle dispersion including dispersing hydrophobic particles, conductive particles and a surfactant of a ferrocene derivative in an aqueous medium, where an oxidized compound in the surfactant of a ferrocene derivative is removed with at least one of an ion exchange resin and a reducing agent. A color filter can be produced in excellent yield without color overlapping by using the micelle dispersion and the process provides the micelle dispersion.
摘要翻译：含有分散在水介质中的疏水性颗粒，导电颗粒和二茂铁衍生物的表面活性剂的胶束分散体。平衡浓度的二茂铁衍生物的表面活性剂含有浓度为40mug / ml以下的氧化化合物，浓度为50〜300mug / ml的还原化合物。一种制备胶束分散体的方法，包括将疏水性颗粒，导电颗粒和二茂铁衍生物的表面活性剂分散在水性介质中，其中二茂铁衍生物的表面活性剂中的氧化化合物用离子交换树脂和还原剂。通过使用胶束分散体，可以以优异的产率制造无色重叠的滤色器，并且该方法提供胶束分散体。

68. 外观设计

USD281877S Cassette tape recorder 失效
公开(公告)号：USD281877S
公开(公告)日：1985-12-24
申请号：US525208
申请日：1983-08-22
申请人： Hideaki Kurata , Kumio Mikami , Hiroshi Matsushima , Isao Wada , Eiko Chikamatsu
设计人： Hideaki Kurata , Kumio Mikami , Hiroshi Matsushima , Isao Wada , Eiko Chikamatsu

69. 外观设计

USD270633S Video disc player 失效
公开(公告)号：USD270633S
公开(公告)日：1983-09-20
申请号：US273811
申请日：1981-06-15
申请人： Hiroshi Shindo , Hideaki Kurata , Hirokazu Hamano
设计人： Hiroshi Shindo , Hideaki Kurata , Hirokazu Hamano

70. 外观设计

USD270632S Video disc player 失效
公开(公告)号：USD270632S
公开(公告)日：1983-09-20
申请号：US273810
申请日：1981-06-15
申请人： Hideaki Kurata , Hirokazu Hamano , Hiroshi Shindo
设计人： Hideaki Kurata , Hirokazu Hamano , Hiroshi Shindo

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