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61. 发明授权

US08101518B2 Method and process for forming a self-aligned silicide contact 有权
标题翻译：用于形成自对准硅化物接触的方法和工艺
公开(公告)号：US08101518B2
公开(公告)日：2012-01-24
申请号：US12136885
申请日：2008-06-11
申请人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
发明人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。在退火步骤A期间，与绝缘材料（例如SiO 2和Si 3 N 4）直接接触的金属不会转化为金属合金硅化物接触。然后进行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

62. 发明申请

US20110253980A1 Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process 有权
标题翻译：碳纳米管/石墨烯CMOS单源自对准金属硅化物工艺的源/排水技术
公开(公告)号：US20110253980A1
公开(公告)日：2011-10-20
申请号：US12762832
申请日：2010-04-19
申请人： Josephine B. Chang , Christian Lavoie , Zhen Zhang
发明人： Josephine B. Chang , Christian Lavoie , Zhen Zhang
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/0665 , H01L29/45 , H01L29/66628 , H01L29/66742 , H01L29/775 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L51/0048 , H01L51/105
摘要： Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.
摘要翻译：提供了具有碳基材料的电子器件和用于与电子器件中的碳基材料接触的技术。一方面，提供一种具有碳基材料的装置; 以及与包含金属硅化物，锗化锗或锗硅化物的碳基材料的至少一个电接触。碳基材料可包括石墨烯或碳纳米管。该装置还可以包括具有杂质的偏析区域，从金属硅化物，锗化锗或锗硅化物中分离碳基材料，其中该杂质具有不同于金属硅化物，锗化锗或锗硅酸盐的功函数。还提供了一种用于制造该装置的方法。

63. 发明授权

US08039382B2 Method for forming self-aligned metal silicide contacts 有权
标题翻译：用于形成自对准金属硅化物接触的方法
公开(公告)号：US08039382B2
公开(公告)日：2011-10-18
申请号：US12539660
申请日：2009-08-12
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

64. 发明授权

US08030154B1 Method for forming a protection layer over metal semiconductor contact and structure formed thereon 失效
标题翻译：用于在金属半导体接触和其上形成的结构上形成保护层的方法
公开(公告)号：US08030154B1
公开(公告)日：2011-10-04
申请号：US12849223
申请日：2010-08-03
申请人： Ahmet S. Ozcan , Christian Lavoie , Zhen Zhang , Bin Yang
发明人： Ahmet S. Ozcan , Christian Lavoie , Zhen Zhang , Bin Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.
摘要翻译：在一个实施例中，提供了一种形成半导体器件的方法，其包括在半导体衬底上提供栅极结构。侧壁间隔件可以与栅极结构相邻地形成。可以在栅极结构的上表面和与栅极结构相邻的半导体衬底的暴露表面上形成金属半导体合金。将金属半导体合金的上表面转化为含氧保护层。使用对含氧保护层具有选择性的蚀刻来去除侧壁间隔物。应变诱导层形成在栅极结构和半导体表面上，其中应变诱导层的至少一部分与栅极结构的侧壁表面直接接触。在另一个实施方案中，金属半导体合金的含氧保护层通过两阶段退火工艺提供。

65. 发明申请

US20110206934A1 GRAPHENE FORMATION UTILIZING SOLID PHASE CARBON SOURCES 有权
标题翻译：利用固相碳源的石墨形成
公开(公告)号：US20110206934A1
公开(公告)日：2011-08-25
申请号：US12710333
申请日：2010-02-22
申请人： Ageeth A. Bol , Roy A. Carruthers , Jack O. Chu , Alfred Grill , Christian Lavoie , Katherine L. Saenger , James C. Tsang
发明人： Ageeth A. Bol , Roy A. Carruthers , Jack O. Chu , Alfred Grill , Christian Lavoie , Katherine L. Saenger , James C. Tsang
IPC分类号： B32B9/00 , B32B15/04 , B05D3/02
CPC分类号： C01B31/0446 , B82Y30/00 , B82Y40/00 , C01B32/184 , Y10T428/30
摘要： A method for forming a single, few-layer, or multi-layer graphene and structure is described incorporating selecting a substrate having a buried layer of carbon underneath a metal layer, providing an ambient and providing a heat treatment to pass carbon through the metal layer to form a graphene layer on the metal layer surface or incorporating a metal-carbon layer which is heated to segregate carbon in the form of graphene to the surface or chemically reacting the metal in the metal-carbon layer with a substrate containing Si driving the carbon to the surface whereby graphene is formed.
摘要翻译：描述了形成单层，几层或多层石墨烯和结构的方法，其包括选择在金属层下方具有埋藏层的衬底的基底，提供环境并提供热处理以使碳通过金属层以在金属层表面上形成石墨烯层或掺入金属碳层，该金属碳层被加热以将石墨烯形式的碳分离到表面或使金属 - 碳层中的金属与含有驱动碳的Si的基板化学反应到形成石墨烯的表面。

66. 发明授权

US07679164B2 Bipolar transistor with silicided sub-collector 有权
标题翻译：双极晶体管，带硅化子集电极
公开(公告)号：US07679164B2
公开(公告)日：2010-03-16
申请号：US11620242
申请日：2007-01-05
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L27/102
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

67. 发明申请

US20100062597A1 Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers 有权
标题翻译：使用无铅焊料进行倒装芯片的互连并具有改进的反应阻挡层
公开(公告)号：US20100062597A1
公开(公告)日：2010-03-11
申请号：US12587301
申请日：2009-10-05
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
IPC分类号： H01L21/60
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

68. 发明授权

US07618891B2 Method for forming self-aligned metal silicide contacts 有权
标题翻译：用于形成自对准金属硅化物接触的方法
公开(公告)号：US07618891B2
公开(公告)日：2009-11-17
申请号：US11415922
申请日：2006-05-01
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

69. 发明授权

US07598516B2 Self-aligned process for nanotube/nanowire FETs 有权
标题翻译：纳米管/纳米线FET的自对准工艺
公开(公告)号：US07598516B2
公开(公告)日：2009-10-06
申请号：US11031168
申请日：2005-01-07
申请人： Phaedon Avouris , Roy A. Carruthers , Jia Chen , Christophe G. M. M. Detavernier , Christian Lavoie , Hon-Sum Philip Wong
发明人： Phaedon Avouris , Roy A. Carruthers , Jia Chen , Christophe G. M. M. Detavernier , Christian Lavoie , Hon-Sum Philip Wong
IPC分类号： H01L29/775 , H01L29/06
CPC分类号： H01L29/6656 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/665 , H01L29/7833 , H01L51/0048 , H01L51/0541 , Y10S977/847 , Y10S977/938
摘要： A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
摘要翻译：互补金属氧化物半导体（CMOS）器件，例如场效应晶体管（FET），其包括通常为碳基纳米材料的至少一个一维纳米结构作为器件沟道，以及金属碳化物接触描述与设备的栅极区域自对准的步骤。本发明还提供一种制造这种CMOS器件的方法。

70. 发明申请

US20090152590A1 METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS 审中-公开
标题翻译：具有硅锗沉积物的半导体器件的方法和结构
公开(公告)号：US20090152590A1
公开(公告)日：2009-06-18
申请号：US11955488
申请日：2007-12-13
申请人： Thomas N. Adam , Linda Black , Huajie Chen , Dureseti Chidambarrao , Robert E. Davis , Judson R. Holt , Randolph F. Knarr , Christian Lavoie , Robert J. Purtell , Dominic J. Schepis
发明人： Thomas N. Adam , Linda Black , Huajie Chen , Dureseti Chidambarrao , Robert E. Davis , Judson R. Holt , Randolph F. Knarr , Christian Lavoie , Robert J. Purtell , Dominic J. Schepis
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636
摘要： A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided.
摘要翻译：一种形成半导体器件的方法，包括在硅 - 锗的第一沉积物上形成硅 - 锗的第二沉积物，所述第一沉积物形成在所述半导体器件的衬底的导电末端区域中并且具有第一百分比的锗，以及所述第二沉积物具有小于所述第一百分比的第二百分比的锗，并且在所述第二沉积物上支持形成硅化物沉积物。还提供了一种结构。

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