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61. 发明专利

JPH0388357A SEMICONDUCTOR MODULE CARRIER 失效
公开(公告)号：JPH0388357A
公开(公告)日：1991-04-12
申请号：JP22481389
申请日：1989-08-31
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI , SHIMADA OSAMU , SUDO TOSHIO , KIMIJIMA SUSUMU , MIYAGI TAKESHI , ITO KENJI , IZEKI YUJI , KUDO JUNICHI
IPC分类号： H05K13/02 , H01L25/00
摘要： PURPOSE:To achieve three-dimensional mounting by performing electrical connection using resilient contact pieces in a sandwiching relation, and engaging and integrating a cylindrical casing body with a coupling part provided on the end surface side of said body. CONSTITUTION:There are disposed in a semiconductor module mounting/holding part 6 resilient contact pieces 9, e.g. a leaf spring, which are electrically connected with lead terminals (I/O terminals) led out along the peripheral part of a semiconductor module 2 and have a function to fix the semiconductor module 2 to fix the semiconductor at its peripheral part, and which are electrically connected with an internal wiring 10 buried in the side wall of an insulating casing body 5. Further, there are disposed coupling parts 11 at a plurality of parts on opposite open end surfaces of the insulating casing body 5, on which coupling parts 11 there is provided a connection terminal part 12 which is disposed on the side wall part of the insulating casing body 5 and from which there is led out the internal wiring 10 which electrically connects to the resilent contact pieces 9. Hereby, semiconductor modules can electrically be connected without use of wire bonding, and further they can integrally be combined electrically with semiconductor module carriers being connected with each other.

62. 发明专利

JPH0237829A CURRENT SOFT SWITCH CIRCUIT 失效
公开(公告)号：JPH0237829A
公开(公告)日：1990-02-07
申请号：JP18932788
申请日：1988-07-27
申请人： TOSHIBA CORP
发明人： ITO KENJI
IPC分类号： G11B15/52 , H03K17/16 , H03K17/60
摘要： PURPOSE:To generate a soft switch current by a bipolar transistor by setting the voltage range of the change period of an input voltage to change slowly from a capacitor in an action area where the voltage current converting characteristics of differential amplifying transistors show linearity. CONSTITUTION:One end of a capacitor C1 in connected to the base of one transistor Q1 of the differential amplifying transistor and a constant voltage source VB is connected to the base of the other transistor Q2. Consequently, when the capacitor C1 is charged with a current from a current source I1 and outputs a saturation voltage, when a switching signal turns high-level, the capacitor C1 is discharged by I2 and the base input voltage of the transistor Q1 is decreased linearly. Here, since the voltage current converting characteristics of the differential amplifying transistors Q1 and Q2 have a linear proportional relationship, the collector current of the Q2 becomes a soft switch current to increase by the linearly inclined characteristic. Thus, a soft current switching can be executed by only the bipolar transistor.

63. 发明专利

JPS6490865A TRAIN OPERATION MANAGING SYSTEM 失效
公开(公告)号：JPS6490865A
公开(公告)日：1989-04-07
申请号：JP24614487
申请日：1987-09-30
申请人： TOSHIBA CORP
发明人： SAITO HIROO , ITO KENJI , OGAWA SHINICHIRO
IPC分类号： B61L25/02 , B61L27/00
摘要： PURPOSE:To facilitate functional confirmation of system by comparing advancing distance of a vehicle with the length of track circuit set for every signal section and obtaining an existing rail position information, thereby enabling simulation of various controls necessary for operation of train based on the information. CONSTITUTION:When the entire system is checked, a simulator 6 is connected through a switch (not shown) with a CPU 11 in a central command station. CPU 16 obtains a speed frequency with respect to vehicle speed for every traveling time and the length for single speed pulse which are stored respectively in a memory section 62. Then traveling distance L of vehicle is obtained based on data read out from the memory section 62 and compared with the lengths of respective track circuits set for every signal section to provide an existing position information on the track circuit which is provided from a digital output section 64 to CPU 11. Realistic control simulation can be realized based on a control command fed from CPU 11.

64. 发明专利

JPS6466854A MAGNETIC RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPS6466854A
公开(公告)日：1989-03-13
申请号：JP22335187
申请日：1987-09-07
申请人： TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG
发明人： ITO KENJI , NAGASAWA MAKOTO
IPC分类号： G11B15/52
摘要： PURPOSE:To control a tape speed with high accuracy in simple constitution by controlling a driving motor in its drive in response to a control signal detected by a detecting means. CONSTITUTION:The titled device is equipped with a magnetic head 11, a wave shaping circuit 12, a leading edge detecting circuit 13, an AND circuit 14, a mask circuit 15, a speed detecting circuit 16, a filter 17, a motor driving amplifier 18 and a driving motor 19. Then, when a leading edge is once inputted out of an inputted waveform signal S4 to the mask circuit 15, its output S4 is then held at an L level for a fixed time only, and a control signal to be inputted is herein masked, and its acceptance is prohibited. For this, irrespective of any tape traveling mode, the wave S4 is inputted always at a fixed periodical interval to the speed detecting circuit 16, and the drive motor 19 is controlled in its drive in accordance with a tape traveling mode, based on an input signal by the motor driving amplifier 18. By this method, the tape speed can be controlled with high accuracy with simple constitution.

65. 发明专利

JPS63166075A DETECTION CIRCUIT FOR PULSE WIDTH 失效
公开(公告)号：JPS63166075A
公开(公告)日：1988-07-09
申请号：JP31535686
申请日：1986-12-26
申请人： TOSHIBA CORP
发明人： ITO KENJI
IPC分类号： G11B20/10 , G11B27/28
摘要： PURPOSE:To detect pulse width even when a tape is fed without using a capstan motor, by comparing the output of a measuring means at the timing of the completing edge of a signal pulse with a shift output, and identifying two kinds of pulse width. CONSTITUTION:A reproducing control signal (CTL) synchronized with a clock (CK) is supplied further to a trailing edge detection circuit 37, and the completing edge of a pulse is detected. The output is supplied to a flip-flop circuit 38 as a sampling pulse, and at the detecting timing of a trailing edge, the Q output of a flip-flop circuit 35 is read in the flip-flop circuit 38. In this case, a counted value at the timing of the completing edge of the pulse is larger than the shift output if the pulse width is larger than a half cycle, and the counted value is smaller than the shift output if it is smaller than the half cycle. Therefore, by comparing the counted value at the timing of the completing edge of the pulse with the shift output, it is possible to identify the pulse width.

66. 发明专利

JPS6335007A FILTER CIRCUIT 失效
公开(公告)号：JPS6335007A
公开(公告)日：1988-02-15
申请号：JP17910386
申请日：1986-07-30
申请人： TOSHIBA CORP
发明人： ITO KENJI
IPC分类号： H03H19/00
摘要： PURPOSE:To decrease the chip size and to reduce the cost by switching a peak detection capacitor and a frequency of a clock to drive a switched capacitor filter (SCF) in time division. CONSTITUTION:With a clock CP2 at a high level, a frequency component fH is extracted by the SCF 22, its peak value is given to a capacitor 26 and a capacitor 27 is in the holding state. On the other hand, with the clock CP 2 at a low level, a frequency component 3fH is extracted by the SCF 22, its peak value is given to the capacitor 27 and the capacitor 26 is in the holding state. Since the frequency components of fH, 3fH are obtained by time division, a tracking error signal SE being a difference of both detection output includes the frequency component of the clock but no problem arises therewith by selecting the frequency of the clock CP 2 sufficiently higher than the operating band of the detection output. Thus, the SCF 22 obtaines the peak value of the two frequency components.

67. 发明专利

JPS6231215A MONOSTABLE MULTIVIBRATOR CIRCUIT 失效
公开(公告)号：JPS6231215A
公开(公告)日：1987-02-10
申请号：JP17077285
申请日：1985-08-02
申请人： TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG
发明人： ITO KENJI , KOBAYASHI TAKAHIRO
IPC分类号： H03K3/0232 , H03K3/023 , H03K5/04
摘要： PURPOSE:To reduce the number of external parts at the formation of an integrated circuit and to attain an essential operation independently of the resistance value of a variable resistor by newly adding a NAND circuit and an AND circuit to a conventional circuit. CONSTITUTION:The NAND circuit 2 and the AND circuit 10 are added. When a trigger pulse is inputted to an input terminal 1, a waveform differentiated by the leading edge of the trigger pulse is generated from the output 18 of a NAND circuit 4. When the resistance value of the variable resistor 12 is turned to '0', the output 21 of a comparator 14 is always kept at 'H'. The output 21 becomes an output 19 always kept at 'H' through an inverter circuit 16 and a NAND circuit 6 and a D-type FF 7 is held at the reset status, so that the output 20 of an inverter circuit 8 is always kept at 'H'. The NAND circuit 2 finds out NAND logic between the trigger pulse and the output 21 and generates an output 23 kept at 'H'. The AND circuit 10 finds out AND between the output 23 and the output of the circuit 8 and outputs the final output to a terminal 17. Thus, a conventional externally fixed resistor can be removed.

68. 发明专利

JPS61150470A VERTICAL SYNCHRONIZING SEPARATOR CIRCUIT 失效
公开(公告)号：JPS61150470A
公开(公告)日：1986-07-09
申请号：JP27175884
申请日：1984-12-25
申请人： TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG
发明人： ITO KENJI , KOBAYASHI TAKAHIRO
IPC分类号： H04N5/10
摘要： PURPOSE:To eliminate jitter components and to decrease the number of pins and external parts with the IC conversion of a vertical synchronizing separator circuit, by detecting the count value of an up-down counter and comparing this count value with the prescribed value for detection of a vertical synchronizing position. CONSTITUTION:A clock input terminal 6 is connected to an input terminal at the other side of an AND circuit 4, and the output terminal of the circuit 4 is connected to a clock terminal CK of an up-down counter 7 of a 4-bit structure. At the same time, a terminal 1 is connected to an up-down count switch terminal R of the counter 7. The output terminal of a NAND circuit 5 is connected to a reset input terminal R of the counter 7, and output terminals Q0-Q3 of the counter 7 are connected to a count value coincidence detecting circuit 8. An output terminal Q3 of the highest bit of the counter 7 is connected to a clock input terminal of a D.FF2 as well as an input terminal at the other side of a NAND circuit 3. A reset terminal R of a D.FF10 is connected to the output terminal of the circuit 8 via an amplifier circuit 9. Then a reverse output terminal -Q of the D.FF10 is connected to a D input terminal of a D.FF11.

69. 发明专利

JPS5754423A Frequency comparison and detection circuit 失效
标题翻译：空值
公开(公告)号：JPS5754423A
公开(公告)日：1982-03-31
申请号：JP13048580
申请日：1980-09-19
申请人： Toshiba Corp
发明人： MOTAI MASAHIKO , ITO KENJI
IPC分类号： H03K5/26
CPC分类号： H03K5/26
摘要： PURPOSE:To discriminate signal frequencies with very simple constitution, by finally shifting and outputting the state of left and right ends according to the difference between right and left shifts in a left and right shift register. CONSTITUTION:When a signal is inputted only to an input terminal 12, since a fixed information 1 set to the 2nd input terminal of an AND circuits 16a is transferred from a latch circuit 19a to 19c, 1 appears at an output termianl 20. Inversely, when the signal enters an input terminal 11 only, a fixed information 0 set to the end input terminal of an AND circuit 18b is transferred from 19c to 19a, 0 appears at a terminal 20. If the frequency of a right shift signal f2 is greater than the left signal frequency f1, the period when an output terminal Q2 is at 1 is gradually longer and finally 1's are consecutive. Inversely, if f1>f2, the period when the terminal Q2 is gradually 0 is longer and finally the terminal potential reaches 0.
摘要翻译：目的：以非常简单的结构来辨别信号频率，通过根据左右移位寄存器的左右移位差最终移位和输出左右端的状态。构成：当信号仅输入到输入端子12时，由于设置到AND电路16a的第二输入端子的固定信息1从锁存电路19a至19c传送，所以出现在输出端子20处。相反，当信号仅输入到输入端子11时，设置到AND电路18b的结束输入端的固定信息0从19c传送到19a，0出现在端子20处。如果右移信号f2的频率较大与左信号频率f1相比，输出端子Q2为1的期间逐渐变长，最后1秒连续。相反，如果f1> f2，则端子Q2逐渐变为0的周期较长，最终端电位达到0。

70. 发明专利

JP2009289821A Semiconductor device and production method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009289821A
公开(公告)日：2009-12-10
申请号：JP2008138390
申请日：2008-05-27
申请人： Toshiba Corp , 株式会社東芝
发明人： MASHITA HIROMITSU , KOTANI TOSHIYA , MUKAI HIDEFUMI , ITO KENJI
IPC分类号： H01L21/8247 , H01L21/027 , H01L21/3205 , H01L23/52 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device securing a focus margin in a lithography process without lowering the device characteristics and enhancing the forming precision of a pattern.
SOLUTION: The semiconductor device 1 is constituted of: a first device pattern 4 provided in a first region 3 on a semiconductor substrate 2; a second device pattern 13 electrically connected with the first pattern 4 and provided in a second region 12 adjacent to the first region 3; a dummy pattern 15 provided between the second pattern 13 and the substrate 2 for aligning the height of the top face of the first pattern 4 with the height of the top face of the second pattern 13 by covering a difference of the height of the second pattern 13 from the height of the first pattern 4; a plotting pattern 20 provided in an interface part between the first region 3 and the second region 12; a first semiconductor element 5 based on the first pattern 4; and a second semiconductor element 14 in which a difference in characteristics due to a structural difference from the first semiconductor element 5 is corrected based on the second pattern 13.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供在光刻工艺中确保焦距的半导体器件，而不降低器件特性并提高图案的成形精度。解决方案：半导体器件1由设置在半导体衬底2上的第一区域3中的第一器件图案4构成; 与第一图案4电连接并设置在与第一区域3相邻的第二区域12中的第二装置图案13; 设置在第二图案13和基板2之间的虚设图案15，用于通过覆盖第二图案的高度的差异来将第一图案4的顶面的高度与第二图案13的顶面的高度对齐 13从第一模式4的高度; 设置在第一区域3和第二区域12之间的界面部分中的绘制图案20; 基于第一图案4的第一半导体元件5; 以及第二半导体元件14，其中基于第二图案13来校正由于与第一半导体元件5的结构差异引起的特性差异。第二模块13（C）2010，JPO＆INPIT

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