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1. 发明专利

JPH0613529A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0613529A
公开(公告)日：1994-01-21
申请号：JP16594392
申请日：1992-06-24
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI
IPC分类号： H01L23/538 , B29C45/14 , H01L23/12 , H01L23/522
摘要： PURPOSE:To suppress reduction in wiring area of a thin-film multilayer wiring layer, and to facilitate the emission of heat from a mounted semiconductor element without inducing complicated operations or cost increase. CONSTITUTION:A semiconductor element 18 is positioned on a die pad 16 disposed on the main surface of a thin-film multilayer wiring plate 9, and that element is also electrically connected to a connecting electrode pad 15 exposed to the outside on the main surface. A built-in heat transfer layer 12 led to the outside via a heat sink terminal 17 is arranged on the same outer surface of the wiring plate 9 where the element 18 is disposed, and the heat transfer layer is connected, in a heat transferring manner, to the die pad 16 on which the element 18 is mounted.

2. 发明专利

JPH0513496A MOUNTING METHOD OF SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH0513496A
公开(公告)日：1993-01-22
申请号：JP15827491
申请日：1991-06-28
申请人： TOSHIBA CORP
发明人： AOKI HIDEO , KOBARIKAWA TAKASHI
IPC分类号： H01L21/60 , H05K3/34
摘要： PURPOSE:To provide a face-down mounting method of a semiconductor element, where a joint excellent in reliability, almost free from imperfect connection, and excellent in bonding strength, can be formed so as to cope with shortening the distance between electrode terminals attendant on the miniaturization and the enhancement of the semiconductor element in functions. CONSTITUTION:In a mounting method where an input-output electrode terminal 2 of a semiconductor element 1 is mounted on a connection pad 4 provided onto a circuit board 3 as aligned making its front surface face toward the board 3, the connection pad 4 provided onto the surface of the circuit board 3 is formed into a protrudent shape 13. A ring-shaped protrusion 11 so formed as to enable the protrusion 13 provided to the connection pad 4 to fit in it is set recessed in the longitudinal section, a low-melting metal 12 is provided to the recess concerned and made to reflow to connect and mount the element 1 onto the board 3 making the front surface of the element 1 face downward.

3. 发明专利

JPH09205103A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09205103A
公开(公告)日：1997-08-05
申请号：JP1017996
申请日：1996-01-24
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI
IPC分类号： H01L23/36 , H01L21/52
摘要： PROBLEM TO BE SOLVED: To avoid the drop in yield due to a lowered viscosity of an adhesive, to simplify the viscosity control of the adhesive, and to reduce the frequency of replacement of the adhesive by providing a storing portion for holding an adhesive flowed out on the top surface of a substrate located at the outer periphery of a semiconductor chip. SOLUTION: When coating a constant amount of a conductive adhesive 7 to an attaching portion 12 of a radiator 11, an excessive amount of the conductaive adhesive sometimes flows out to the vicinities of the attaching portion 12, or the adhesive sometimes flows out to the vicinities of the attaching portion 12 when the conductive adhesive 7 is heated and hardened after coating or putting the whole in an oven. Therefore, a storing portion 13 made of a recessed groove is provided around the attaching portion 12, the conductive adhesive 7 flowed out is stored in the storing portion 13, the outflow of the adhesive to an electrode pad 8 formed on a circuit substrate 1 or between leads of a tape carrier package 10 is eliminated, and electrical shortcircuit by the conductive adhesive 7 can be prevented. Therefore, the drop in the yield due to a lowered viscosity of the adhesive can be avoided.

4. 发明专利

JPH0613754A MANUFACTURE OF MULTILAYER WIRING BOARD 失效
公开(公告)号：JPH0613754A
公开(公告)日：1994-01-21
申请号：JP16594592
申请日：1992-06-24
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI
IPC分类号： H05K3/46
摘要： PURPOSE:To easily obtain a multilayer wiring board which possesses and displays required functions and high reliability, where Cu circuit patterns interconnected in multilayer and a polyimide resin insulating layer are firmly joined into one piece, and chemical compounds are prevented from being produced. CONSTITUTION:A circuit pattern 4 of Cu is formed on the primary surface of an insulating base board through the intermediary of an adhesive metal layer 3 in a first process, the exposed face of the Cu circuit pattern 4 is oxidized to form a Cu oxide layer 4a, in a second process, polyamic acid resin is applied to the Cu circuit pattern 4 having the Cu oxide layer 4a in a third process, and the polyamic acid resin layer on the Cu oxide layer 4a is turned into a polyimide resin layer 5 through a curing treatment in a fourth process.

5. 发明专利

JPH08203905A METHOD OF FORMING SOLDER BUMP 失效
公开(公告)号：JPH08203905A
公开(公告)日：1996-08-09
申请号：JP980095
申请日：1995-01-25
申请人： TOSHIBA CORP
发明人： KIMIJIMA SUSUMU , YAMAMOTO TOSHIO , MORI IKUO , KOBARIKAWA TAKASHI
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE: To enable solder bumps to be formed at low cost by a method wherein solder formed in sheetlike shape is put on a substrate and melted and bonded onto electrodes. CONSTITUTION: In order to form solder bumps on the electrodes of a substrate 10 whereon the electrodes 11 are provided, the solder 31 formed in sheetlike shape is put on the substrate 10 and melted and bonded onto the electrodes 11. For example, a barrier metal 13 is formed on substrate electrodes 11 and then the semiconductor substrate 10 excluding the electrodes 11 is coated with a passivation film 12 while the electrodes 11 are coated with flux 20. Next, the solder sheet 31 is put on the semiconductor substrate 10 and after fixing the solder sheet 31 on the semiconductor substrate 10 by use of the viscosity of the flux 30, the positions corresponding to the barrier metal 13 are irradiated with a laser beam so as to melt the solder sheet 31 on the irradiated parts.

6. 发明专利

JPH07235768A PRODUCTION PROCESS FOR THIN FILM MULTILAYER WIRING BOARD 失效
公开(公告)号：JPH07235768A
公开(公告)日：1995-09-05
申请号：JP2796294
申请日：1994-02-25
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI
IPC分类号： H05K3/24 , H05K3/40 , H05K3/46
摘要： PURPOSE:To form a thick-film wiring pattern and reduce the 'pitch thereof by forming a conductor film on a first thin film insulation pattern forming face, thereby forming one electrode, and building up the conductor by the electroplating to make it flush with the pattern top face whereby a second thin film insulation resin pattern having required via-holes is formed. CONSTITUTION:A surface with a conductor layer 10 formed thereon is patterned to expose a wiring pattern forming region, thereby forming a plating-resist pattern 11a on a first resin insulator layer 9a. Using the layer 10a as a plating electrode, the wiring pattern forming region is built up with a conductor so as to be flush with the layer 9a, thereby forming a first wring pattern layer 12a. A polyimide resin layer is formed as a second resin insulation layer 9b having openings 9b' far forming pier connection parts. Thus, the forming of the inner layer insulation resin layer can be repeated enough to meet the performance of high-speed LSI's.

7. 发明专利

JPH08213399A METHOD FOR FORMING SOLDER BUMP 失效
公开(公告)号：JPH08213399A
公开(公告)日：1996-08-20
申请号：JP2064995
申请日：1995-02-08
申请人： TOSHIBA CORP
发明人： KIMIJIMA SUSUMU , YAMAMOTO TOSHIO , MORI IKUO , KOBARIKAWA TAKASHI
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE: To provide a method for forming solder bumps by which homogeneous bumps having uniform sizes can be formed. CONSTITUTION: A method for forming solder bumps by which solder bumps are respectively formed on the electrodes 11 of a semiconductor substrate 10 provided with the electrodes 11 contains at least a supply process for supplying solder 20 onto the electrodes 11, polishing process for polishing the supplied solder 20 to a prescribed height from the surface of the substrate 10, and bump forming process for forming the solder bumps 21 by melting the solder 20a by heating.

8. 发明专利

JPH06188568A THIN FILM MULTILAYER WIRING BOARD 失效
公开(公告)号：JPH06188568A
公开(公告)日：1994-07-08
申请号：JP33869292
申请日：1992-12-18
申请人： TOSHIBA CORP
发明人： KONO CHIE , KOBARIKAWA TAKASHI
IPC分类号： H05K3/46
摘要： PURPOSE:To provide the title thin film multilayer wiring board discharging the function of avoiding the damage and breakage of an insulating layer by mechanism shock during wire-bonding step, etc., fit for the structure of highly reliable multichip module, etc. CONSTITUTION:Within the title thin film multilayer board with an insulating supporting board 4 whose surface is partly insulated electrically, a conductor wiring layer and an inorganic base insulating layer integrally formed and arranged to be alternately laminated on the main surface of the insulating supporting board 4, a multilayer wiring part 5 incorporating a capacitor comprising from a ground layer 5c to a power supply layer 5a and a bonding pad 6 formed and arranged on a specific area on the surface of the multilayer wiring part 5, a shock resistant buffer material layer 5e is to be inserted and arranged in either inner layer insulating layer 5b between the ground layer 5c and power supply layer 5a comprising the capacitor of the multilayer wiring part 5 and the bonding pad 6.

9. 发明专利

JPH0689844A ALIGNER 失效
公开(公告)号：JPH0689844A
公开(公告)日：1994-03-29
申请号：JP24065992
申请日：1992-09-09
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI
IPC分类号： G02B17/00 , G03F7/20 , G03F7/207 , H01L21/027 , H01L21/30 , H05K3/00
摘要： PURPOSE:To acquire a reflective projection type exposure device with a function which enables arbitrary selection and setting of a projection magnification to an exposure object surface of a pattern mask by considering an error of a dimensional accuracy caused by contraction property (contraction coefficient) involved in burning. CONSTITUTION:This device is provided with an exposure source 9 for shedding light on a specified surface of a pattern mask 8 and a luminous flux magnification conversion lens group 10 for converting magnification of luminous flux which passes through the pattern mask 8. The device is further provided with a first optical path conversion mirror 12 which guides transmitted luminous flux converted to a specified luminous flux magnification by any of the lens group 10 to a concave mirror 11, a convex lens 13 which is arranged in opposition to the concave mirror 11 and reflects light reflected at the concave mirror 11 to the concave mirror 11 again and a second optical path conversion mirror 15 which guides the reflected light which is reflected by the convex mirror 13 and reflected again by the concave mirror 11 to a surface of an exposure object 14.

10. 发明专利

JPH0574856A MOUNTING METHOD OF SEMICONDUCTOR CHIP 失效
公开(公告)号：JPH0574856A
公开(公告)日：1993-03-26
申请号：JP23583291
申请日：1991-09-17
申请人： TOSHIBA CORP
发明人： KOBARIKAWA TAKASHI , AOKI HIDEO
IPC分类号： H01L21/60
摘要： PURPOSE:To reduce a thermal stress exerted on a connecting part by a method wherein the connecting part of an electrode to an electrode pad takes a shape supported by a resin. CONSTITUTION:Electrodes 1a for connection use on a semiconductor chip 1 and electrode pads 3a on a circuit board 3 which correspond to each other are connected electrically via corresponding conductor regions 7 which are buried and installed so as to pass a resin plate 5. That is to say, the conductor regions which form (participate in the connection of) connecting parts of the electrodes to the electrode pads present shapes supported by a resin. Since the connecting parts are formed to be comparatively longer compared with the case of their connection via bumps, a thermal stress exerted on the connecting parts can be reduced easily. Consequently, it is possible to always achieve a required face-down mounting operation without causing a drop in reliability by fatigue destruction or the like.

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