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61. 发明申请

US20090032817A1 Back-To-Back Metal/Semiconductor/Metal (MSM) Schottky Diode 有权
标题翻译：背对背金属/半导体/金属（MSM）肖特基二极管
公开(公告)号：US20090032817A1
公开(公告)日：2009-02-05
申请号：US12234663
申请日：2008-09-21
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L29/04 , H01L21/329
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

62. 发明申请

US20090008647A1 Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers 失效
标题翻译：使用多个铝化合物缓冲层的氮化镓 - 硅 - 硅界面
公开(公告)号：US20090008647A1
公开(公告)日：2009-01-08
申请号：US11825427
申请日：2007-07-06
申请人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L29/15 , H01L21/20
CPC分类号： H01L29/155 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L21/0262 , H01L21/02647 , H01L29/2003 , H01L29/205
摘要： A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0
摘要翻译：已经提供了使用多种铝化合物缓冲层的硅（Si）和氮化镓（GaN）膜之间的热膨胀界面，以及相关的制造方法。该方法提供（111）Si衬底，并通过将衬底加热至1000至1200℃的较高温度，将衬底上的第一层AlN沉积在衬底上。在第一层AlN上沉积第二层AlN，较低温度为500至800℃。通过将衬底加热到较高温度范围，沉积第三层AlN，覆盖第二层AlN。然后，形成覆盖在第一层次Al1-XGaXN层上的固定组成Al1-XGaXN层的覆盖在第三层AlN上的分级Al1-XGaXN层，其中0

63. 发明申请

US20080296625A1 Gallium nitride-on-silicon multilayered interface 审中-公开
标题翻译：氮化镓 - 硅多层界面
公开(公告)号：US20080296625A1
公开(公告)日：2008-12-04
申请号：US11810022
申请日：2007-06-04
申请人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02458 , H01L21/02461 , H01L21/02463 , H01L21/02488 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L21/02642 , H01L21/02647
摘要： A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process.
摘要翻译：提供硅（Si）和氮化镓（GaN）膜之间的多层热膨胀界面以及相关的制造方法。该方法提供（111）Si衬底并且形成覆盖衬底的第一膜的第一层。将Si衬底加热至约300至800℃的温度，并且第二膜的第一层以压缩形式覆盖第一膜的第一层。使用横向纳米外延过度生长（LNEO）工艺，生长第一GaN层，覆盖第一层第二层膜。然后，重复上述过程：形成第二层第一膜; 将基板加热至约300至800℃的温度; 在压缩中形成第二层第二膜; 并且使用LNEO工艺生长第二GaN层。

64. 发明申请

US20080296616A1 Gallium nitride-on-silicon nanoscale patterned interface 审中-公开
标题翻译：氮化镓 - 硅纳米尺度图案化界面
公开(公告)号：US20080296616A1
公开(公告)日：2008-12-04
申请号：US11809958
申请日：2007-06-04
申请人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/20 , H01L29/20
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02458 , H01L21/02461 , H01L21/02463 , H01L21/0251 , H01L21/02513 , H01L21/0254 , H01L21/02639 , H01L21/02642 , H01L21/02647
摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al1−xGaxN (0
摘要翻译：提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。该方法提供加热至约300至800℃范围内的温度的（111）Si衬底，并且第一膜以压缩形式覆盖Si衬底。第一膜材料可以是InP，SiGe，GaP，GaAs，AlN，AlGaN，AlN /分级AlGaN（Al1-xGaxN（0

65. 发明授权

US07402456B2 PCMO thin film with memory resistance properties 有权
标题翻译：具有记忆电阻特性的PCMO薄膜
公开(公告)号：US07402456B2
公开(公告)日：2008-07-22
申请号：US10831677
申请日：2004-04-23
申请人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
发明人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
摘要翻译：提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。在一个方面，第一晶体结构是无定形或弱结晶。然后，响应于单极脉冲改变PCMO膜的电阻状态。另一方面，PCMO薄膜具有多晶结构。然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

66. 发明申请

US20080164577A1 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US20080164577A1
公开(公告)日：2008-07-10
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。最后，去除Si 3 N 4 N 4管。

67. 发明授权

US07259055B2 Method of forming high-luminescence silicon electroluminescence device 失效
标题翻译：形成高发光硅电致发光器件的方法
公开(公告)号：US07259055B2
公开(公告)日：2007-08-21
申请号：US11066713
申请日：2005-02-24
申请人： Tingkai Li , Pooran Chandra Joshi , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Pooran Chandra Joshi , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L31/03046 , Y02E10/544 , Y02P70/521
摘要： A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).
摘要翻译：提供一种用于形成高发光Si电致发光（EL）荧光体的方法，其具有由Si荧光体制成的EL器件。该方法包括：用Si纳米晶体沉积富含氧的氧化物（SRO）膜，折射率在1.5至2.1范围内，孔隙率在5至20％的范围内; 并且在氧气氛中对SRO膜进行后退火。 DC溅射或PECVD工艺可用于沉积SRO膜。在一个方面，该方法还包括：HF缓冲氧化物蚀刻（BOE）SRO膜; 并且再次氧化SRO膜，以在SRO膜中的Si纳米晶体周围形成SiO 2层。在一个方面，SRO膜通过在氧气气氛中退火再次氧化。以这种方式，在具有1至5纳米（nm）范围内的厚度的Si纳米晶体周围形成SiO 2层。

68. 发明授权

US07008801B2 Method of forming ferroelectric thin films on a high-k layer 失效
公开(公告)号：US07008801B2
公开(公告)日：2006-03-07
申请号：US10453831
申请日：2003-06-02
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

69. 发明授权

US06939724B2 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
公开(公告)号：US06939724B2
公开(公告)日：2005-09-06
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

70. 发明授权

US06927074B2 Asymmetric memory cell 有权
标题翻译：不对称记忆单元
公开(公告)号：US06927074B2
公开(公告)日：2005-08-09
申请号：US10442627
申请日：2003-05-21
申请人： Sheng Teng Hsu , Tingkai Li , David R. Evans
发明人： Sheng Teng Hsu , Tingkai Li , David R. Evans
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L21/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/15 , G11C2213/31 , G11C2213/52 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147
摘要： An asymmetric memory cell and method for forming an asymmetric memory cell are provided. The method comprises: forming a bottom electrode having a first area; forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode; forming a top electrode overlying the EPVR layer having a second area, less than the first area. In some aspects the second area is at least 20% smaller than the first area. The EPVR is a material such as colossal magnetoresistance (CMR), high temperature super conducting (HTSC), or perovskite metal oxide materials. The method further comprises: inducing an electric field between the electrodes; inducing current flow through the EPVR adjacent the top electrode; and, in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR. Typically, the resistance is modified within the range of 100 ohms to 10 mega-ohms.
摘要翻译：提供了一种用于形成非对称存储单元的非对称存储单元和方法。该方法包括：形成具有第一区域的底部电极; 形成覆盖底部电极的各种电阻（EPVR）材料的电脉冲; 形成覆盖在EPVR层上的顶部电极，其具有小于第一区域的第二区域。在一些方面，第二区域比第一区域小至少20％。 EPVR是诸如巨磁阻（CMR），高温超导（HTSC）或钙钛矿金属氧化物材料的材料。该方法还包括：在电极之间引入电场; 通过邻近顶部电极的EPVR引起电流流动; 并且响应于通过与顶部电极相邻的EPVR的电流流动，修改EPVR的电阻。通常，电阻在100欧姆到10兆欧姆的范围内被修改。

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