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61. 发明授权

US08200607B2 Memory devices and data decision methods 有权
标题翻译：内存设备和数据决策方法
公开(公告)号：US08200607B2
公开(公告)日：2012-06-12
申请号：US12292539
申请日：2008-11-20
申请人： Jae Hong Kim , Heeseok Eun , Yong June Kim , Jun Jin Kong , Seung-Hwan Song
发明人： Jae Hong Kim , Heeseok Eun , Yong June Kim , Jun Jin Kong , Seung-Hwan Song
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06N99/005
摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.
摘要翻译：公开了一种存储器件和数据判定方法。存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

62. 发明申请

US20100254189A1 Apparatus and method of memory programming 有权
标题翻译：存储器编程的装置和方法
公开(公告)号：US20100254189A1
公开(公告)日：2010-10-07
申请号：US12801532
申请日：2010-06-14
申请人： Kyoung Lea Cho , Yoon Dong Park , Jun Jin Kong , Jong Han Kim , Jae Hong Kim , Young Hwan Lee , Heeseok Eun , Seung-Hwan Song
发明人： Kyoung Lea Cho , Yoon Dong Park , Jun Jin Kong , Jong Han Kim , Jae Hong Kim , Young Hwan Lee , Heeseok Eun , Seung-Hwan Song
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C29/00 , G11C2216/14
摘要： A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.
摘要翻译：提供了存储器编程设备和/或方法。存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。数据存储单元可以被配置为存储数据页。第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。索引存储单元可以被配置为存储所生成的索引信息。编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。第一计数单元可以将生成的索引信息发送到编程单元。存储器编程装置可以监视存储器单元中阈值电压的分布状态。

63. 发明授权

US07835209B2 Method and apparatus for controlling reading level of memory cell 有权
标题翻译：用于控制存储单元的读取电平的方法和装置
公开(公告)号：US07835209B2
公开(公告)日：2010-11-16
申请号：US12003545
申请日：2007-12-28
申请人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/0411
摘要： A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.
摘要翻译：提供了一种用于控制存储单元的读取电平的方法和装置。控制存储器单元的读取电平的方法可以包括：接收基于给定电压电平和参考电平计算出的度量值; 通过对应于来自接收到的度量值中的接收信号的电平的度量值相加来产生每个参考电平的相加值; 从所述参考电平中选择具有所生成的总和值的最大值的参考电平; 以及基于所选择的参考电平来控制所述存储器单元的读取电平。

64. 发明授权

US08458578B2 Apparatus for generating soft decision values using an analog-to-digital converter and method thereof 有权
标题翻译：用于使用模数转换器产生软判决值的装置及其方法
公开(公告)号：US08458578B2
公开(公告)日：2013-06-04
申请号：US11978569
申请日：2007-10-30
申请人： Sung Chung Park , Jun Jin Kong , Seung Jae Lee , Seung-Hwan Song
发明人： Sung Chung Park , Jun Jin Kong , Seung Jae Lee , Seung-Hwan Song
IPC分类号： H03M13/03 , H03M13/00
CPC分类号： H04L25/067 , H04L27/06 , H04L27/22
摘要： According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.
摘要翻译：根据示例实施例，使用具有给定分辨率的模数转换器（ADC）产生软判决值的方法可以包括基于传输信号的电平和ADC的输出电平来计算的度量值。可以从接收到的度量值中选择与接收信号的电平对应的度量值。当传输位是第一级时，可以从选择的度量值中检测第一最大度量值，并且当传输位是第二级时，可以从所选择的度量值中检测第二最大度量值。可以基于第一最大度量值和第二最大度量值之间的差异来生成软判决值。

65. 发明申请

US20080288853A1 Apparatus and method of puncturing of error control codes 审中-公开
标题翻译：打孔错误控制代码的设备和方法
公开(公告)号：US20080288853A1
公开(公告)日：2008-11-20
申请号：US11889410
申请日：2007-08-13
申请人： Jun Jin Kong , Jong Han Kim , Hong Rak Son , Young Hwan Lee , Sung Chung Park , Seung-Hwan Song
发明人： Jun Jin Kong , Jong Han Kim , Hong Rak Son , Young Hwan Lee , Sung Chung Park , Seung-Hwan Song
IPC分类号： H03M13/03
CPC分类号： H03M13/6362
摘要： A code puncturing apparatus and method is provided. The apparatus includes: a codeword selection unit selecting continuous n−1-number of mother codewords from mother codewords generated from k-bit effective information, where k denotes a natural number, and one redundancy bit; and a puncturing unit selecting k-number of redundancy bits from redundancy bits included in the n−1-number of mother codewords, deleting remaining redundancy bits, and rearranging the n−1-number of mother codewords into an n·k bit-target codeword. Accordingly, a code rate of an Error Control Code (ECC) can be raised.
摘要翻译：提供了一种代码穿刺装置和方法。该装置包括：码字选择单元，从k比特有效信息生成的母码中选择连续n-1个母码字，其中k表示自然数，一个冗余比特; 以及删截单元，从包含在n-1个母码字中的冗余比特中选择k个冗余比特，删除剩余的冗余比特，并将n-1个母码字重排为nk比特目标码字。因此，可以提高错误控制码（ECC）的码率。

66. 发明申请

US20080288849A1 Apparatus for generating soft decision values and method thereof 有权
标题翻译：用于产生软判决值的装置及其方法
公开(公告)号：US20080288849A1
公开(公告)日：2008-11-20
申请号：US11978569
申请日：2007-10-30
申请人： Sung Chung Park , Jun Jin Kong , Seung Jae Lee , Seung-Hwan Song
发明人： Sung Chung Park , Jun Jin Kong , Seung Jae Lee , Seung-Hwan Song
IPC分类号： H03M13/45 , G06F11/00
CPC分类号： H04L25/067 , H04L27/06 , H04L27/22
摘要： According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.
摘要翻译：根据示例实施例，使用具有给定分辨率的模数转换器（ADC）产生软判决值的方法可以包括基于传输信号的电平和ADC的输出电平来计算的度量值。可以从接收到的度量值中选择与接收信号的电平对应的度量值。当传输位是第一级时，可以从选择的度量值中检测第一最大度量值，并且当传输位是第二级时，可以从所选择的度量值中检测第二最大度量值。可以基于第一最大度量值和第二最大度量值之间的差异来生成软判决值。

67. 发明申请

US20080320064A1 Method and apparatus for controlling reading level of memory cell 有权
标题翻译：用于控制存储单元的读取电平的方法和装置
公开(公告)号：US20080320064A1
公开(公告)日：2008-12-25
申请号：US12003545
申请日：2007-12-28
申请人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
IPC分类号： G06F1/16
CPC分类号： G11C16/28 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/0411
摘要： A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.
摘要翻译：提供了一种用于控制存储单元的读取电平的方法和装置。控制存储器单元的读取电平的方法可以包括：接收基于给定电压电平和参考电平计算出的度量值; 通过对应于来自接收到的度量值中的接收信号的电平的度量值相加来产生每个参考电平的相加值; 从所述参考电平中选择具有所生成的总和值的最大值的参考电平; 以及基于所选择的参考电平来控制所述存储器单元的读取电平。

68. 发明授权

US08607118B2 Iterative decoding method and apparatus 有权
标题翻译：迭代解码方法和装置
公开(公告)号：US08607118B2
公开(公告)日：2013-12-10
申请号：US12475640
申请日：2009-06-01
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
摘要翻译：公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在迭代次数的执行期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

69. 发明申请

US20110249495A1 NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICES HAVING THE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件，其操作方法和具有非易失性存储器件的器件
公开(公告)号：US20110249495A1
公开(公告)日：2011-10-13
申请号：US13071727
申请日：2011-03-25
申请人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
发明人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels. One of the plurality of states of the second group of states includes at least one of the plurality of states of the first group of states.
摘要翻译：提供了一种非易失性存储器件。非易失性存储器件包括存储单元阵列，其包括多个多电平单元，每个多电平单元存储与第一组状态的多个状态中的一个对应的数据，以及控制电路。控制电路被配置为根据第一组验证电压电平的第一验证电压电平对第一多电平单元中的多个状态中的一个状态进行编程的数据，并且控制第一多电平单元被重新根据第二验证电压电平组的第一验证电压电平编程为第二组状态的多个状态中的一个状态。第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。第二组状态的多个状态之一包括第一组状态的多个状态中的至少一个状态。

70. 发明授权

US08004891B2 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US08004891B2
公开(公告)日：2011-08-23
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

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