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1. 发明申请

US20090234792A1 Memory devices and data decision methods 有权
标题翻译：内存设备和数据决策方法
公开(公告)号：US20090234792A1
公开(公告)日：2009-09-17
申请号：US12292539
申请日：2008-11-20
申请人： Jae Hong Kim , Heeseok Eun , Yong June Kim , Jun Jin Kong , Seung-Hwan Song
发明人： Jae Hong Kim , Heeseok Eun , Yong June Kim , Jun Jin Kong , Seung-Hwan Song
IPC分类号： G06N5/00
CPC分类号： G06N99/005
摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.
摘要翻译：公开了一种存储器件和数据判定方法。存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

2. 发明授权

US08200607B2 Memory devices and data decision methods 有权
标题翻译：内存设备和数据决策方法
公开(公告)号：US08200607B2
公开(公告)日：2012-06-12
申请号：US12292539
申请日：2008-11-20
申请人： Jae Hong Kim , Heeseok Eun , Yong June Kim , Jun Jin Kong , Seung-Hwan Song
发明人： Jae Hong Kim , Heeseok Eun , Yong June Kim , Jun Jin Kong , Seung-Hwan Song
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06N99/005
摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.
摘要翻译：公开了一种存储器件和数据判定方法。存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

3. 发明授权

US08345487B2 Method of setting read voltage minimizing read data errors 有权
标题翻译：设置读取电压最小化读取数据错误的方法
公开(公告)号：US08345487B2
公开(公告)日：2013-01-01
申请号：US12774814
申请日：2010-05-06
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son , Seung-Hwan Song
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son , Seung-Hwan Song
IPC分类号： G11C11/413
CPC分类号： G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.
摘要翻译：一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

4. 发明申请

US20100115225A1 Memory Device and Memory System Including the Same 审中-公开
标题翻译：内存设备和包含其的内存系统
公开(公告)号：US20100115225A1
公开(公告)日：2010-05-06
申请号：US12577842
申请日：2009-10-13
申请人： Jaehong Kim , Heeseok Eun , Yong June Kim , Seung-Hwan Song
发明人： Jaehong Kim , Heeseok Eun , Yong June Kim , Seung-Hwan Song
IPC分类号： G06F12/00
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0679 , G11C11/5621 , G11C16/349
摘要： Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed.
摘要翻译：提供了一种存储器件。存储器件包括字线和连接到字线的多个存储器单元。多个存储单元形成页面，并且可以改变构成页面的扇区数量和每个扇区的大小。

5. 发明授权

US07864574B2 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US07864574B2
公开(公告)日：2011-01-04
申请号：US12453108
申请日：2009-04-29
申请人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
发明人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及第二个数据页面。

6. 发明授权

US08773922B2 Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data 失效
标题翻译：非易失性存储器件，存储卡和系统，以及通过将参考程序数据与比较读取数据进行比较来确定读取电压的方法
公开(公告)号：US08773922B2
公开(公告)日：2014-07-08
申请号：US12614545
申请日：2009-11-09
申请人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
发明人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
IPC分类号： G11C7/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.
摘要翻译：公开了一种非易失性半导体存储器件及确定读取电压的相关方法。非易失性半导体存储器件包括：包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

7. 发明申请

US20090285023A1 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US20090285023A1
公开(公告)日：2009-11-19
申请号：US12453108
申请日：2009-04-29
申请人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
发明人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
IPC分类号： G11C16/02 , G11C7/00 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及第二个数据页面。

8. 发明授权

US09158500B2 Device and method for processing data including generating a pseudo random number sequence 有权
标题翻译：用于处理数据的装置和方法，包括产生伪随机数序列
公开(公告)号：US09158500B2
公开(公告)日：2015-10-13
申请号：US13537297
申请日：2012-06-29
申请人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
发明人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
摘要翻译：一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

9. 发明授权

US08972775B2 Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit 有权
标题翻译：存储器件和管理存储器数据错误的方法，包括基于校正的误差位确定验证电压和改变阈值电压
公开(公告)号：US08972775B2
公开(公告)日：2015-03-03
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/07 , G11C16/10 , G06F11/10 , G11C11/56 , G11C16/34 , G11C29/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

10. 发明授权

US08713411B2 Encoding and/or decoding memory devices and methods thereof 有权
标题翻译：编码和/或解码存储器件及其方法
公开(公告)号：US08713411B2
公开(公告)日：2014-04-29
申请号：US12232258
申请日：2008-09-12
申请人： Jun Jin Kong , Yong June Kim , Jae Hong Kim
发明人： Jun Jin Kong , Yong June Kim , Jae Hong Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/03 , G06F11/1072 , H03M13/05
摘要： Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.
摘要翻译：可以提供编码/解码存储器件及其方法。根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

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