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1. 发明授权

US08508990B2 Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device 有权
标题翻译：非易失性存储器件，其操作方法以及具有非易失性存储器件的器件
公开(公告)号：US08508990B2
公开(公告)日：2013-08-13
申请号：US13071727
申请日：2011-03-25
申请人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
发明人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454
摘要： A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.
摘要翻译：非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个多电平单元，每个多电平单元存储对应于第一组状态的多种状态之一的数据，以及控制电路。控制电路被配置为根据第一组验证电压电平的第一验证电压电平对与第一多电平单元中的多个状态中的一个状态相对应的数据，并且将第一多电平单元控制为根据第二组验证电压电平的第一验证电压电平，将其重新编程为第二组状态的多个状态之一。第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。

2. 发明申请

US20110249495A1 NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICES HAVING THE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件，其操作方法和具有非易失性存储器件的器件
公开(公告)号：US20110249495A1
公开(公告)日：2011-10-13
申请号：US13071727
申请日：2011-03-25
申请人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
发明人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels. One of the plurality of states of the second group of states includes at least one of the plurality of states of the first group of states.
摘要翻译：提供了一种非易失性存储器件。非易失性存储器件包括存储单元阵列，其包括多个多电平单元，每个多电平单元存储与第一组状态的多个状态中的一个对应的数据，以及控制电路。控制电路被配置为根据第一组验证电压电平的第一验证电压电平对第一多电平单元中的多个状态中的一个状态进行编程的数据，并且控制第一多电平单元被重新根据第二验证电压电平组的第一验证电压电平编程为第二组状态的多个状态中的一个状态。第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。第二组状态的多个状态之一包括第一组状态的多个状态中的至少一个状态。

3. 发明授权

US08972775B2 Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit 有权
标题翻译：存储器件和管理存储器数据错误的方法，包括基于校正的误差位确定验证电压和改变阈值电压
公开(公告)号：US08972775B2
公开(公告)日：2015-03-03
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/07 , G11C16/10 , G06F11/10 , G11C11/56 , G11C16/34 , G11C29/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

4. 发明授权

US08479085B2 Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
标题翻译：具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量
公开(公告)号：US08479085B2
公开(公告)日：2013-07-02
申请号：US12191458
申请日：2008-08-14
申请人： Nam Phil Jo , Jun Jin Kong , Chan Ho Yoon , Dong Hyuk Chae , Kyoung Lae Cho
发明人： Nam Phil Jo , Jun Jin Kong , Chan Ho Yoon , Dong Hyuk Chae , Kyoung Lae Cho
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G11C7/1006 , G11C2029/0411
摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
摘要翻译：存储器系统包括：包括纠错解码器的存储器控制器。纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

5. 发明授权

US08347194B2 Hierarchical decoding apparatus 有权
标题翻译：分层解码装置
公开(公告)号：US08347194B2
公开(公告)日：2013-01-01
申请号：US12428511
申请日：2009-04-23
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： G06F11/00
CPC分类号： H03M13/2906 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/1194 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/296 , H03M13/3707 , H03M13/3738
摘要： A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
摘要翻译：解码器包括多个解码器级和控制器。解码器级使用相应的不同解码算法对接收到的信号执行解码操作。控制器确定解码器中的一个相对于接收信号执行的解码操作是否成功，并且响应于确定的结果来控制每个其他解码器级的解码操作。

6. 发明授权

US07843727B2 Memory device and data reading method 有权
标题翻译：存储器和数据读取方式
公开(公告)号：US07843727B2
公开(公告)日：2010-11-30
申请号：US12232138
申请日：2008-09-11
申请人： Kyoung Lae Cho , Donghun Yu , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim , Heeseok Eun
发明人： Kyoung Lae Cho , Donghun Yu , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim , Heeseok Eun
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/3418 , G11C29/00
摘要： A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first group and second group, reads data of the first group from the memory page, and determines a scheme of reading data of the second group from the memory page based on the read data of the first group.
摘要翻译：提供存储器件和存储器数据读取方法。存储器件可以包括：多位单元阵列; 编程单元，其将N个数据页存储在多位单元阵列中的存储器页面中; 以及控制单元，其将N个数据页划分为第一组和第二组，从存储器页面读取第一组的数据，并且基于读取的数据确定从存储器页面读取第二组的数据的方案第一组。

7. 发明授权

US07706181B2 Multi-bit programming device and method using single-bit memory cells 有权
标题翻译：多位编程设备和使用单位存储单元的方法
公开(公告)号：US07706181B2
公开(公告)日：2010-04-27
申请号：US11896349
申请日：2007-08-31
申请人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要： A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译：提供了一种用于非易失性存储器的多位编程设备和方法。在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元，以及备份编程单元，被配置为选择备份相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

8. 发明申请

US20090222701A1 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US20090222701A1
公开(公告)日：2009-09-03
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

9. 发明申请

US20090190396A1 Memory device and method of reading memory data 有权
标题翻译：存储器件和读取存储器数据的方法
公开(公告)号：US20090190396A1
公开(公告)日：2009-07-30
申请号：US12219264
申请日：2008-07-18
申请人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
发明人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/34 , G11C11/5642 , G11C2211/5634
摘要： A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.
摘要翻译：可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。存储器件可以包括多比特单元阵列，其包括至少一个存储器页，每个存储器页具有多个多位单元，以及确定单元，用于将多个多位单元划分成第一组和第二组。第一组可以包括具有高于参考电压的阈值电压的多位单元。第二组可以包括阈值电压低于参考电压的多位单元。确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。

10. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

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