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1. 发明授权

US08667365B2 Flash memory system that uses an interleaving scheme for increasing data transfer performance between a memory device and a controller and a method therof 有权
标题翻译：闪存系统使用交织方案来增加存储设备和控制器之间的数据传输性能以及方法
公开(公告)号：US08667365B2
公开(公告)日：2014-03-04
申请号：US12256784
申请日：2008-10-23
申请人： Nam Phil Jo , Dong Hyuk Chae , Sung Chung Park , Dong Gu Kang
发明人： Nam Phil Jo , Dong Hyuk Chae , Sung Chung Park , Dong Gu Kang
IPC分类号： G06F11/00
CPC分类号： G11C7/1042 , G06F11/1068 , G06F13/4239
摘要： A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.
摘要翻译：存储器系统包括多个存储器件，被配置为控制多个存储器件的控制器以及连接在多个存储器件与控制器之间的至少一个通道。所述至少一个通道包括与所述多个存储器件连接的输入/输出数据线和控制信号线以及分别连接到所述多个存储器件中的每一个的芯片使能信号线，其中所述芯片使能信号线使得能够多个存储设备独立。控制器向多个存储器件之一发送读取命令或程序命令，并且当多个存储器件中的一个存储器件响应于读取命令执行内部读取操作时，控制器从另一个多个存储器件，或者当多个存储器件中的一个存储器件响应于程序命令执行内部程序操作时，控制器将数据编程到多个存储器件中的另一个。

2. 发明授权

US08499217B2 Memory device and error control codes decoding method 有权
公开(公告)号：US08499217B2
公开(公告)日：2013-07-30
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： H03M13/00 , G06F11/00 , G11C29/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

3. 发明授权

US08122329B2 Methods of operating memory devices using error correction and rereading techniques 有权
标题翻译：使用纠错和重新读取技术来操作存储器件的方法
公开(公告)号：US08122329B2
公开(公告)日：2012-02-21
申请号：US12929161
申请日：2011-01-05
申请人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
发明人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G11C29/42 , G06F11/1068 , G11C11/5628 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.
摘要翻译：提供各种读取级别控制装置和方法。在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及读数据。该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

4. 发明申请

US20110145663A1 Read level control apparatuses and methods 有权
标题翻译：读取电平控制装置和方法
公开(公告)号：US20110145663A1
公开(公告)日：2011-06-16
申请号：US12929161
申请日：2011-01-05
申请人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
发明人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
IPC分类号： G06F11/00
CPC分类号： G11C29/42 , G06F11/1068 , G11C11/5628 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.
摘要翻译：提供各种读取级别控制装置和方法。在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及读数据。该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

5. 发明授权

US07835209B2 Method and apparatus for controlling reading level of memory cell 有权
标题翻译：用于控制存储单元的读取电平的方法和装置
公开(公告)号：US07835209B2
公开(公告)日：2010-11-16
申请号：US12003545
申请日：2007-12-28
申请人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/0411
摘要： A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.
摘要翻译：提供了一种用于控制存储单元的读取电平的方法和装置。控制存储器单元的读取电平的方法可以包括：接收基于给定电压电平和参考电平计算出的度量值; 通过对应于来自接收到的度量值中的接收信号的电平的度量值相加来产生每个参考电平的相加值; 从所述参考电平中选择具有所生成的总和值的最大值的参考电平; 以及基于所选择的参考电平来控制所述存储器单元的读取电平。

6. 发明授权

US07782666B2 Apparatus and method of multi-bit programming 有权
标题翻译：多位编程的装置和方法
公开(公告)号：US07782666B2
公开(公告)日：2010-08-24
申请号：US12076392
申请日：2008-03-18
申请人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Seung Hoon Lee , Jung Hun Sung , Sung-Jae Byun , Seung-Hwan Song , Donghun Yu , Sung Chung Park , Heeseok Eun
发明人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Seung Hoon Lee , Jung Hun Sung , Sung-Jae Byun , Seung-Hwan Song , Donghun Yu , Sung Chung Park , Heeseok Eun
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2N threshold voltage states to the N-bit data; a second control unit that spaces, by any one of a first interval and a second interval, adjacent threshold voltage states of the 2N threshold voltage states; and a programming unit that programs the N-bit data by generating, in each of the at least one multi-bit cell, a distribution state corresponding to the allocated threshold voltage state. The multi-bit programming apparatus can reduce an error rate when reading data.
摘要翻译：提供了多位编程设备和/或方法。多比特编程装置可以包括：第一控制单元，其向N比特数据分配2N个阈值电压状态中的任何一个; 第二控制单元，其以第一间隔和第二间隔中的任一个间隔相邻的阈值电压状态的阈值电压状态; 以及编程单元，其通过在所述至少一个多位单元中的每一个中生成与所分配的阈值电压状态相对应的分布状态来对所述N位数据进行编程。多位编程装置可以在读取数据时降低错误率。

7. 发明申请

US20090103359A1 Apparatus and method of multi-bit programming 有权
标题翻译：多位编程的装置和方法
公开(公告)号：US20090103359A1
公开(公告)日：2009-04-23
申请号：US12073101
申请日：2008-02-29
申请人： Seung-Hwan SONG , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
发明人： Seung-Hwan SONG , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5621
摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.
摘要翻译：提供了多位编程设备和/或方法。多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

8. 发明申请

US20080151621A1 Multi-level cell memory devices and methods of storing data in and reading data from the memory devices 有权
标题翻译：多级单元存储器件以及将数据存储在存储器件中并从其读取数据的方法
公开(公告)号：US20080151621A1
公开(公告)日：2008-06-26
申请号：US11802656
申请日：2007-05-24
申请人： Jun Jin Kong , Sung Chung Park , Dong Ku Kang , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun
发明人： Jun Jin Kong , Sung Chung Park , Dong Ku Kang , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.
摘要翻译：多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。

9. 发明申请

US20080137414A1 Multi-level cell memory device and method thereof 有权
标题翻译：多级单元存储装置及其方法
公开(公告)号：US20080137414A1
公开(公告)日：2008-06-12
申请号：US11808173
申请日：2007-06-07
申请人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
IPC分类号： G11C7/10
CPC分类号： G11C11/5621 , G11C7/1006 , G11C29/00
摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
摘要翻译：提供了一种多级单元（MLC）存储器件及其方法。示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。

10. 发明申请

US20080056392A1 Dual carrier modulation (DCM) demapper and DCM demapping method 有权
标题翻译：双载波调制（DCM）解映射器和DCM解映射方法
公开(公告)号：US20080056392A1
公开(公告)日：2008-03-06
申请号：US11704907
申请日：2007-02-12
申请人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
发明人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
IPC分类号： H04K1/10 , H03D1/00
CPC分类号： H04L27/2649 , H04L25/022 , H04L25/067 , H04L27/3416
摘要： A DCM demapper and a DCM demapping method are provided. The DCM demapper includes: a basic signal generation unit generating a plurality of basic signals using a signal and channel information of two subcarriers; a soft decision generation unit generating a plurality of soft decisions using the plurality of basic signals; and a soft decision selection unit selecting a soft decision corresponding to each bit of the two subcarriers among the generated soft decisions.
摘要翻译：提供DCM解映射器和DCM解映射方法。 DCM解映射器包括：使用信号和两个子载波的信道信息生成多个基本信号的基本信号生成单元; 软判决生成单元，使用所述多个基本信号生成多个软判决; 以及软判决选择单元，在所生成的软决策中选择与所述两个子载波的每个比特相对应的软判决。

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