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61. 发明申请

US20050262368A1 Link power saving state 有权
标题翻译：链路省电状态
公开(公告)号：US20050262368A1
公开(公告)日：2005-11-24
申请号：US10850733
申请日：2004-05-21
申请人： Naveen Cherukuri , Jeffrey Wilcox , Sanjay Dabral , Phanindra Mannava , Aaron Spink , David Dunning , Tim Frodsham , Theodore Schoenborn
发明人： Naveen Cherukuri , Jeffrey Wilcox , Sanjay Dabral , Phanindra Mannava , Aaron Spink , David Dunning , Tim Frodsham , Theodore Schoenborn
IPC分类号： G06F1/26 , G06F1/32 , H04L12/12
CPC分类号： G06F1/3209 , G06F1/3253 , H04L12/12 , Y02D10/151 , Y02D50/20 , Y02D50/40
摘要： Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.
摘要翻译：公开了用于点对点链路的低功率状态的方法，装置和系统的实施例。在低功率状态期间，差分发送对的两个导体上的信号被驱动到电气空闲。模拟活动检测器在低功率状态期间被使能，并且在正常功率状态期间被禁用。退出低功耗状态不需要物理层重新初始化的顺序。还描述和要求保护其他实施例。

62. 发明申请

US20050262284A1 Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link 有权
标题翻译：用于识别通过链路连接的两个CSI代理的不良通道和交换宽度能力的方法
公开(公告)号：US20050262284A1
公开(公告)日：2005-11-24
申请号：US10851925
申请日：2004-05-21
申请人： Naveen Cherukuri , Sanjay Dabral , David Dunning , Tim Frodsham , Theodore Schoenborn , Rahul Shah , Maurice Steinman
发明人： Naveen Cherukuri , Sanjay Dabral , David Dunning , Tim Frodsham , Theodore Schoenborn , Rahul Shah , Maurice Steinman
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4265
摘要： A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.
摘要翻译：描述了一种技术，其中具有使用系统中的点对点互连耦合在一起的端口的两个链路代理交换其链路宽度支持能力并协商相互同意的链路宽度。每对代理之间的互连包括具有多个电线或通道的一对单向链路，其中一个链路被第一代理用于向第二代理传输数据，另一链路由第二代理使用，数据到第一代理。

63. 发明申请

US20050259599A1 Technique for lane virtualization 有权
标题翻译：车道虚拟化技术
公开(公告)号：US20050259599A1
公开(公告)日：2005-11-24
申请号：US10891348
申请日：2004-07-13
申请人： Naveen Cherukuri , Jeffrey Wilcox , Sanjay Dabral , David Dunning , Tim Frodsham , Theodore Schoenborn
发明人： Naveen Cherukuri , Jeffrey Wilcox , Sanjay Dabral , David Dunning , Tim Frodsham , Theodore Schoenborn
IPC分类号： G06F13/38 , G06F13/40 , H04L12/26 , H04L12/28 , H04L29/08
CPC分类号： G06F13/4018 , G06F13/4009 , Y02D10/14 , Y02D10/151
摘要： A technique to perform virtualization of lanes within a common system interface (CSI) link. More particularly, embodiments described herein relate to virtualizing interconnective paths between two or more electronic devices residing in an electronic network.
摘要翻译：在公共系统接口（CSI）链路中执行通道虚拟化的技术。更具体地，这里描述的实施例涉及虚拟化驻留在电子网络中的两个或多个电子设备之间的互连路径。

64. 发明授权

US06905526B1 Fabrication of an ion exchange polish pad 失效
标题翻译：制造离子交换抛光垫
公开(公告)号：US06905526B1
公开(公告)日：2005-06-14
申请号：US09993575
申请日：2001-11-06
申请人： Sanjay Dabral , Anil K. Pant
发明人： Sanjay Dabral , Anil K. Pant
IPC分类号： B24B37/04 , B24D3/34 , B24D7/02 , B24D3/02 , C09C1/68 , C09K3/14
CPC分类号： B24B37/22 , B24D3/344 , B24D7/02
摘要： Embodiments of the invention include an ion exchange polish pad for polishing a semiconductor substrate, on which various conductive, semiconductive, and/or insulative layers are formed, for example a conductive copper layer. Embodiments also include the method for the manufacture of an ion exchange polish pad. In certain embodiments an ion exchange polish pad includes a base material and a ion exchange layer including, which further includes an ion exchange material. Cations in the ion exchange material may be exchanged with other cations, such as copper, under the proper process conditions for the planarization of a processed semiconductor substrate.
摘要翻译：本发明的实施例包括用于抛光半导体衬底的离子交换抛光垫，其上形成有各种导电，半导体和/或绝缘层，例如导电铜层。实施例还包括用于制造离子交换抛光垫的方法。在某些实施方案中，离子交换抛光垫包括基材和离子交换层，所述离子交换层还包括离子交换材料。离子交换材料中的阳离子可以在适当的工艺条件下与其它阳离子例如铜交换，以便对被处理的半导体衬底进行平坦化。

65. 发明授权

US06777975B1 Input-output bus interface to bridge different process technologies 失效
标题翻译：输入输出总线接口来桥接不同的工艺技术
公开(公告)号：US06777975B1
公开(公告)日：2004-08-17
申请号：US09451684
申请日：1999-11-30
申请人： Sanjay Dabral , Ming Zeng , Ramesh Senthinathan , Andrew M. Volk
发明人： Sanjay Dabral , Ming Zeng , Ramesh Senthinathan , Andrew M. Volk
IPC分类号： H03K1716
CPC分类号： G06F13/4086
摘要： A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.
摘要翻译：一种总线，其中传输线由具有连接到传输线并且具有核心电压VCC的源的pMOSFET激发，并且其中传输线由连接到地的设备终止。

66. 发明授权

US06773337B1 Method and apparatus to recondition an ion exchange polish pad 失效
标题翻译：修复离子交换抛光垫的方法和装置
公开(公告)号：US06773337B1
公开(公告)日：2004-08-10
申请号：US09993809
申请日：2001-11-06
申请人： Sanjay Dabral , Anil K. Pant
发明人： Sanjay Dabral , Anil K. Pant
IPC分类号： B24B100
CPC分类号： B24B53/017 , B24B37/042 , B24D3/344 , B24D7/02
摘要： In certain embodiments of the invention an ion exchange polish pad, which is used for polishing Copper layers formed on a semiconductor substrate, may be conditioned and/or reconditioned to regenerate its binding capacity for cations. Once bound to an ion exchange polish pad, cations for example may be exchanged for protons (H+) by exposing the ion exchange polish pad to a reconditioning medium(s). The exchange of cations with H+ reconditions the ion exchange material of an ion exchange polish pad so it is capable of binding and removing additional cations from a surface. In certain embodiments, a reconditioning head is used to recondition an ion exchange polish pad. A typical reconditioning process comprises elution of bound copper from ion exchange polish pad followed by protonation. Elution of bound copper may be accomplished by exposing an ion exchange polish pad to a strong acid solution, or similar chemical treatments.
摘要翻译：在本发明的某些实施方案中，用于抛光形成在半导体衬底上的铜层的离子交换抛光垫可以被调理和/或再生以再生其对阳离子的结合能力。一旦结合到离子交换抛光垫上，阳离子例如可以通过将离子交换抛光垫暴露于修复介质来交换质子（H +）。用H +交换阳离子重新调整离子交换抛光垫的离子交换材料，使其能够从表面结合和除去附加的阳离子。在某些实施例中，使用修复头来重新调整离子交换抛光垫。典型的修复方法包括从离子交换抛光垫洗脱结合的铜，然后质子化。结合铜的洗脱可以通过将离子交换抛光垫暴露于强酸溶液或类似的化学处理来实现。

67. 发明授权

US06722950B1 Method and apparatus for electrodialytic chemical mechanical polishing and deposition 失效
标题翻译：电渗析化学机械抛光和沉积的方法和装置
公开(公告)号：US06722950B1
公开(公告)日：2004-04-20
申请号：US09993807
申请日：2001-11-06
申请人： Sanjay Dabral , Anil K. Pant
发明人： Sanjay Dabral , Anil K. Pant
IPC分类号： B24B100
CPC分类号： B24B53/017 , B23H5/08 , B24B37/042 , B24B37/046 , B24D3/344 , B24D7/02 , H01L21/32125 , H01L21/7684 , Y10S451/908
摘要： Embodiments of the invention include methods and apparatus for electrodialytic polishing of various layers formed on semiconductor substrates. In certain embodiments the use of electrodialytic processes in conjunction with chemical mechanical forces to achieve a copper interconnect with a desired level of planarity and process performance. In certain embodiments electrodialytic polishing uses an electrodialytic polish pad, which is an active pad which has copper binding groups provided in its core structure and has an added capability of allowing electrical conductivity. An electrodialytic polish pad allows transfer of cations or anions through a membrane in the presence of an electric field and into a cathodic electrolyte. Under the influence of an electric field the electrodialytic polish pad and/or electrodialytic pads are continuously refreshed to bind cations.
摘要翻译：本发明的实施例包括用于在半导体衬底上形成的各种层的电渗析的方法和装置。在某些实施方案中，使用电渗析方法结合化学机械力来实现具有期望水平的平面性和工艺性能的铜互连。在某些实施方案中，电渗析抛光使用电渗析抛光垫，其为具有在其核心结构中提供的铜结合基团并具有允许导电性的附加能力的活性垫。电渗透抛光垫允许阳离子或阴离子在电场存在下通过膜转移到阴极电解质中。在电场的影响下，电渗析抛光垫和/或电渗析垫不断刷新以结合阳离子。

68. 发明授权

US06715111B2 Method and apparatus for detecting strobe errors 有权
标题翻译：用于检测频闪错误的方法和装置
公开(公告)号：US06715111B2
公开(公告)日：2004-03-30
申请号：US09748233
申请日：2000-12-27
申请人： Keith Self , Michael Sandhinti , Sanjay Dabral
发明人： Keith Self , Michael Sandhinti , Sanjay Dabral
IPC分类号： G06F1100
CPC分类号： G06F11/0745 , G06F11/076
摘要： A method and apparatus for detecting data strobe errors. A strobe error detection circuit has a strobe input and a counter coupled to the strobe input to count strobe pulses received. The circuit also has a comparator to determine if a strobe error has occurred based on the magnitude of the difference between a first count of strobe pulses and a second count of strobe pulses. In an embodiment, the first count is read from a memory location at a first time and the second count is read at a second time.
摘要翻译：一种用于检测数据选通错误的方法和装置。选通错误检测电路具有选通输入和耦合到选通输入的计数器以对接收到的选通脉冲进行计数。该电路还具有一个比较器，用于根据第一次选通脉冲计数和第二个选通脉冲计数之间的差值的大小来确定是否发生了选通脉冲错误。在一个实施例中，在第一时间从存储器位置读取第一计数，并且在第二时间读取第二计数。

69. 发明授权

US06661277B2 Enhanced conductivity body biased PMOS driver 失效
标题翻译：增强导电体偏置PMOS驱动器
公开(公告)号：US06661277B2
公开(公告)日：2003-12-09
申请号：US10314309
申请日：2002-12-09
申请人： Sanjay Dabral
发明人： Sanjay Dabral
IPC分类号： H03K301
CPC分类号： H03K19/0027 , H01L29/78 , H03K2217/0018
摘要： According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.
摘要翻译：根据本发明的一个实施例，一种用于偏置晶体管本体的方法。该方法包括检测施加到晶体管的端子的电压，并且基于检测到的电压将偏置电压耦合到身体。

70. 发明授权

US06622256B1 System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof 失效
标题翻译：用于通过将选通信号分离为指针路径和定时路径来保护频闪毛刺的系统，从其指针路径上的信号滤除毛刺
公开(公告)号：US06622256B1
公开(公告)日：2003-09-16
申请号：US09539666
申请日：2000-03-30
申请人： Sanjay Dabral , Alper Ilkbahar
发明人： Sanjay Dabral , Alper Ilkbahar
IPC分类号： G06F104
CPC分类号： H03K5/1252 , H03K5/133 , H03L7/0805 , H03L7/0995 , H04L7/0008 , H04L7/0025 , H04L7/005
摘要： A method and apparatus for a strobe glitch protection mechanism for a source synchronous I/O link. One method of the present invention comprises separating a transfer clock having a plurality of transfer clock edges into a pointer path and a timing path. Glitches are filtered from signals on said pointer path. The pointer path and the timing path are coupled to generate latch enable signals to latch data bits.
摘要翻译：一种用于源同步I / O链路的选通脉冲干扰保护机制的方法和装置。本发明的一种方法包括将具有多个传送时钟边缘的传送时钟分离成指针路径和定时路径。毛刺从所述指针路径上的信号中滤除。指针路径和定时路径被耦合以产生锁存使能信号以锁存数据位。

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