专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050273635A1 Power state coordination between devices sharing power-managed resources 有权
标题翻译：共享权力管理资源的设备之间的电源状态协调
公开(公告)号：US20050273635A1
公开(公告)日：2005-12-08
申请号：US10871638
申请日：2004-06-17
申请人： Jeffrey Wilcox , Shivnandan Kaushik , Stephen Gunther , Devadatta Bodas , Siva Ramakrishnan , David Poisner , Lance Hacking
发明人： Jeffrey Wilcox , Shivnandan Kaushik , Stephen Gunther , Devadatta Bodas , Siva Ramakrishnan , David Poisner , Lance Hacking
IPC分类号： G06F1/26 , G06F1/30 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3246 , G06F1/3287 , Y02D10/171 , Y10T307/438
摘要： Methods and apparatuses for coordination of power state management in and electronic system.
摘要翻译：电力系统管理与电力系统协调的方法与装置。

2. 发明授权

US06185634B2 Address triggered DMA controller with an indicative signal including circuitry for calculating a new trigger address value based on the sum of the current trigger address and the descriptor register data with a trigger address register 失效
标题翻译：地址触发的DMA控制器具有指示信号，包括用于基于当前触发地址和描述符寄存器数据之和与触发地址寄存器计算新的触发地址值的电路
公开(公告)号：US06185634B2
公开(公告)日：2001-02-06
申请号：US08720102
申请日：1996-09-27
申请人： Jeffrey Wilcox
发明人： Jeffrey Wilcox
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： An address triggered DMA controller includes a DMA engine for controlling transfer of data between an external device and locations in a memory designated by respective addresses. Such a DMA controller also includes a DMA monitor for monitoring the respective addresses, and if one of the respective addresses matches a predetermined value, generating a signal to indicate a match.
摘要翻译：地址触发的DMA控制器包括一个DMA引擎，用于控制外部设备之间的数据传输和由各个地址指定的存储器中的位置。这样的DMA控制器还包括用于监视相应地址的DMA监视器，并且如果各个地址中的一个匹配预定值，则生成指示匹配的信号。

3. 发明申请

US20100330927A1 LINK POWER SAVINGS WITH STATE RETENTION 有权
标题翻译：链接节电与状态保持
公开(公告)号：US20100330927A1
公开(公告)日：2010-12-30
申请号：US12495706
申请日：2009-06-30
申请人： Naveen Cherukuri , Jeffrey Wilcox , Venkatraman Iyer , Selim Bilgin , David D. Dunning , Robin Tim Frodsham , Theodore Z. Schoenborn , Sanjay Dabral
发明人： Naveen Cherukuri , Jeffrey Wilcox , Venkatraman Iyer , Selim Bilgin , David D. Dunning , Robin Tim Frodsham , Theodore Z. Schoenborn , Sanjay Dabral
IPC分类号： H04B7/00
CPC分类号： G06F1/3287 , G06F1/3296 , H04W52/0219 , H04W52/0229 , Y02D70/122
摘要： Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
摘要翻译：描述了与链路功率节省与状态保持有关的方法和设备。在一个实施例中，通过串行链路耦合的两个代理的一个或多个组件在空闲时段期间被关闭，同时保持每个代理中的链路状态。还公开了其他实施例。

4. 发明申请

US20080075107A1 LINK POWER SAVING STATE 审中-公开
公开(公告)号：US20080075107A1
公开(公告)日：2008-03-27
申请号：US11950314
申请日：2007-12-04
申请人： Naveen Cherukuri , Jeffrey Wilcox , Sanjay Dabral , Phanindra Mannava , Aaron Spink , David Dunning , Tim Frodsham , Theodore Schoenborn
发明人： Naveen Cherukuri , Jeffrey Wilcox , Sanjay Dabral , Phanindra Mannava , Aaron Spink , David Dunning , Tim Frodsham , Theodore Schoenborn
IPC分类号： H04L12/413
CPC分类号： G06F1/3209 , G06F1/3253 , H04L12/12 , Y02D10/151 , Y02D50/20 , Y02D50/40
摘要： Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

5. 发明申请

US20050262365A1 P-state feedback to operating system with hardware coordination 有权
标题翻译： P状态反馈到操作系统与硬件协调
公开(公告)号：US20050262365A1
公开(公告)日：2005-11-24
申请号：US10850775
申请日：2004-05-21
申请人： Bernard Lint , Alon Naveh , Shivnandan Kaushik , Jeffrey Wilcox , Lance Hacking , Ping Sager , Kushagra Vaid , Todd Dutton
发明人： Bernard Lint , Alon Naveh , Shivnandan Kaushik , Jeffrey Wilcox , Lance Hacking , Ping Sager , Kushagra Vaid , Todd Dutton
IPC分类号： G06F1/26
CPC分类号： G06F11/3419 , G06F11/3452 , G06F11/3466 , G06F2201/88 , Y02D10/34
摘要： A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a pervious period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.
摘要翻译：本文描述了具有硬件协调的对操作系统（OS）的P状态反馈的机制。在一个实施例中，过程的示例包括但不限于从处理器接收表示在一段时间内的平均性能的数据，以及基于下一个时间段确定性能状态（P状态）部分来自表示前一段时间内的平均表现的数据。还描述了其它方法和装置。

6. 发明授权

US08831666B2 Link power savings with state retention 有权
标题翻译：链接省电与状态保留
公开(公告)号：US08831666B2
公开(公告)日：2014-09-09
申请号：US12495706
申请日：2009-06-30
申请人： Naveen Cherukuri , Jeffrey Wilcox , Venkatraman Iyer , Selim Bilgin , David D. Dunning , Robin Tim Frodsham , Theodore Z. Schoenborn , Sanjay Dabral
发明人： Naveen Cherukuri , Jeffrey Wilcox , Venkatraman Iyer , Selim Bilgin , David D. Dunning , Robin Tim Frodsham , Theodore Z. Schoenborn , Sanjay Dabral
IPC分类号： H04B7/00
CPC分类号： G06F1/3287 , G06F1/3296 , H04W52/0219 , H04W52/0229 , Y02D70/122
摘要： Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
摘要翻译：描述了与链路功率节省与状态保持有关的方法和设备。在一个实施例中，通过串行链路耦合的两个代理的一个或多个组件在空闲时段期间被关闭，同时保持每个代理中的链路状态。还公开了其他实施例。

7. 发明申请

US20070118677A1 Packet switch having a crossbar switch that connects multiport receiving and transmitting elements 审中-公开
标题翻译：分组交换机具有连接多端口接收和发送元件的交叉开关
公开(公告)号：US20070118677A1
公开(公告)日：2007-05-24
申请号：US11129250
申请日：2005-05-13
申请人： Ron Swartzentruber , Jeffrey Wilcox
发明人： Ron Swartzentruber , Jeffrey Wilcox
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , H04L49/101 , H04L49/109 , H04L49/201
摘要： An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.
摘要翻译：实现了符合Rapidio网络架构的多个设备的集成电路。集成电路中包含两个提供24个交换端口的RapidIO设备和交换设备。这些设备具有分组接收侧和分组发送侧; 每个设备的分组接收侧由其自己的分组发送侧和每个其他发送侧的被称为极点的128位宽路径连接。集成电路的特征包括集成电路上的所有设备的集中组播和配置控制，在RapidIO设备中具有多于一个地址的规定，用于定义由路由表路由的地址空间的技术，用于管理拥塞的技术，和先进的缓冲管理技术。

8. 发明申请

US20060256793A1 Efficient multi-bank buffer management scheme for non-aligned data 审中-公开
标题翻译：用于不对齐数据的高效多库缓冲管理方案
公开(公告)号：US20060256793A1
公开(公告)日：2006-11-16
申请号：US11129247
申请日：2005-05-13
申请人： Ron Swartzentruber , Jeffrey Wilcox
发明人： Ron Swartzentruber , Jeffrey Wilcox
IPC分类号： H04L12/56
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901 , H04L49/9021
摘要： An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.
摘要翻译：实现了符合Rapidio网络架构的多个设备的集成电路。集成电路中包含两个提供24个交换端口的RapidIO设备和交换设备。这些设备具有分组接收侧和分组发送侧; 每个设备的分组接收侧由其自己的分组发送侧和每个其他发送侧的被称为极点的128位宽路径连接。集成电路的特征包括集成电路上的所有设备的集中多播和配置控制，在RapidIO设备中具有多于一个地址的规定，用于定义由路由表路由的地址空间的技术，用于管理拥塞的技术，和先进的缓冲管理技术。

9. 发明申请

US20060034295A1 Dynamically modulating link width 有权
标题翻译：动态调制链路宽度
公开(公告)号：US20060034295A1
公开(公告)日：2006-02-16
申请号：US10850851
申请日：2004-05-21
申请人： Naveen Cherukuri , Aaron Spink , Phanindra Mannava , Tim Frodsham , Jeffrey Wilcox , Sanjay Dabral , David Dunning , Theodore Schoenborn
发明人： Naveen Cherukuri , Aaron Spink , Phanindra Mannava , Tim Frodsham , Jeffrey Wilcox , Sanjay Dabral , David Dunning , Theodore Schoenborn
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L67/141 , G06F13/4265 , H04L65/60 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.
摘要翻译：管理链路的系统和方法提供了在链路初始化期间接收远程宽度能力，即对应于远程端口的远程宽度能力。根据远程宽度能力，本地端口和远程端口之间的链路以多个链路宽度进行操作。

10. 发明申请

US20050179293A1 SEAT SUSPENSION 审中-公开
标题翻译：座椅暂停
公开(公告)号：US20050179293A1
公开(公告)日：2005-08-18
申请号：US10908167
申请日：2005-04-29
申请人： Jeffrey Wilcox
发明人： Jeffrey Wilcox
IPC分类号： A47C1/02 , A47C7/14 , B60N2/54
CPC分类号： B60N2/502 , A47C7/024 , A47C7/14 , B60N2/544 , B60N2/546
摘要： A seat suspension has a base and a seat support. A foundation extends upwardly at a forward portion of the base. A pair of panels hingedly extends from the foundation, with a spring between each panel and the base. In one embodiment, the panels are hinged to the foundation by a living hinge. In another embodiment, the panels are formed of glass springs, wherein each panel comprises one arm of the spring. In another embodiment, the seat suspension is adjustable.
摘要翻译：座椅悬挂件具有基座和座椅支撑件。基座在基部的前部向上延伸。一对面板从基座铰接地延伸，弹簧在每个面板和基座之间。在一个实施例中，面板通过活动铰链铰接到基座。在另一个实施例中，面板由玻璃弹簧形成，其中每个面板包括弹簧的一个臂。在另一个实施例中，座椅悬挂是可调节的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式