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61. 发明授权

US06440788B2 Implant sequence for multi-function semiconductor structure and method 失效
标题翻译：多功能半导体结构和方法的种植体序列
公开(公告)号：US06440788B2
公开(公告)日：2002-08-27
申请号：US09895159
申请日：2001-07-02
申请人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2710
CPC分类号： H01L29/7302 , H01L21/84 , H01L27/1203
摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
摘要翻译：提供了多功能半导体器件。该器件包括并联形成的双极晶体管和FET。半导体衬底设置在绝缘层上。源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。集电极区域和源极/发射极区域之间的最短距离定义基极宽度。

62. 发明授权

US06429477B1 Shared body and diffusion contact structure and method for fabricating same 失效
标题翻译：共享体和扩散接触结构及其制造方法
公开(公告)号：US06429477B1
公开(公告)日：2002-08-06
申请号：US09702315
申请日：2000-10-31
申请人： Jack A. Mandelman , Rama Divakaruni , William R. Tonti
发明人： Jack A. Mandelman , Rama Divakaruni , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L27/10861 , H01L21/743 , H01L21/76897 , H01L27/0214 , H01L27/10888 , H01L27/1203
摘要： The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity. Additionally, the shared via body contact and diffusion contact can be selectively formed borderless to adjacent gate conductors in the device.
摘要翻译：优选实施例通过提供在用于绝缘体上硅（SOI）技术的单个共享通孔中形成的体接触和扩散接触来克服背景技术中发现的困难。通过在单个共享通孔中形成体接触和扩散接触，器件尺寸最小化并且性能得到改善。特别地，形成的体接触将SOI层与底层衬底连接，以避免由浮动SOI沟道区产生的不稳定性和漏电。形成的扩散触点将器件扩散连接到上述布线以便于器件操作。通过在单个共享通孔中将身体接触和扩散接触提供在一起，优选的实施例避免了由单独接触引起的区域损失。此外，优选实施例提供与其他装置自对准的身体接触，使尽可能少的过程复杂性所需的公差最小化。此外，共享的通孔体接触和扩散接触可以选择性地形成与设备中的相邻栅极导体无边界。

63. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

64. 发明授权

US06255694B1 Multi-function semiconductor structure and method 失效
标题翻译：多功能半导体结构及方法
公开(公告)号：US06255694B1
公开(公告)日：2001-07-03
申请号：US09484198
申请日：2000-01-18
申请人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2701
CPC分类号： H01L29/7302 , H01L21/84 , H01L27/1203
摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
摘要翻译：提供了多功能半导体器件。该器件包括并联形成的双极晶体管和FET。半导体衬底设置在绝缘层上。源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。集电极区域和源极/发射极区域之间的最短距离定义基极宽度。

65. 发明授权

US6163045A Reduced parasitic leakage in semiconductor devices 有权
标题翻译：减少半导体器件中的寄生泄漏
公开(公告)号：US6163045A
公开(公告)日：2000-12-19
申请号：US215011
申请日：1998-12-17
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.
摘要翻译：一种沟槽式电容器，其具有与该套环相邻的扩散区域以增加寄生MOSFET的栅极阈值电压。这使得能够使用更薄的套环，同时仍然实现可接受的泄漏。在一个实施例中，扩散区域是自对准的。

66. 发明授权

US5894152A SOI/bulk hybrid substrate and method of forming the same 失效
公开(公告)号：US5894152A
公开(公告)日：1999-04-13
申请号：US878225
申请日：1997-06-18
申请人： Mark A. Jaso , Jack A. Mandelman , William R. Tonti , Matthew R. Wordeman
发明人： Mark A. Jaso , Jack A. Mandelman , William R. Tonti , Matthew R. Wordeman
IPC分类号： H01L21/20 , H01L21/76 , H01L21/762 , H01L21/84 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/84 , H01L21/7624 , H01L27/1203
摘要： A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

67. 发明申请

US20090147568A1 Memory Elements and Methods of Using the Same 有权
标题翻译：内存元素及其使用方法
公开(公告)号：US20090147568A1
公开(公告)日：2009-06-11
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

68. 发明申请

US20080258857A1 ELECTRONIC FUSE WITH CONFORMAL FUSE ELEMENT FORMED OVER A FREESTANDING DIELECTRIC SPACER 失效
标题翻译：具有合适的保险丝元件的电子保险丝在自动电介质间隔件上形成
公开(公告)号：US20080258857A1
公开(公告)日：2008-10-23
申请号：US12128100
申请日：2008-05-28
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01H85/08
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

69. 发明申请

US20080144252A1 PROGRAMMABLE CAPACITORS AND METHODS OF USING THE SAME 审中-公开
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20080144252A1
公开(公告)日：2008-06-19
申请号：US12037725
申请日：2008-02-26
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H01G7/00
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

70. 发明申请

US20080006855A1 CMOS Devices Adapted to Prevent Latchup and Methods of Manufacturing the Same 失效
标题翻译： CMOS器件适用于防止滞后及其制造方法
公开(公告)号：US20080006855A1
公开(公告)日：2008-01-10
申请号：US11456357
申请日：2006-07-10
申请人： Jack A. Mandelman , William R. Tonti
发明人： Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/743 , H01L21/823814 , H01L21/823878 , H01L27/0921 , H01L29/665 , H01L2027/1189
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是衬底上的半导体器件，其包括：（1）第一金属氧化物半导体场效应晶体管（MOSFET）; （2）耦合到所述第一MOSFET的第二MOSFET，其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管（BJT）; 和（3）将第一或第二MOSFET的源极扩散区域与源极扩散区域下方的掺杂阱区域电耦合的导电区域。导电区域适于防止在环路中形成感应电流。提供了许多其他方面。

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