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61. 发明申请

US20050059252A1 Self-aligned planar double-gate process by self-aligned oxidation 有权
标题翻译：自对准平面双栅极工艺通过自对准氧化
公开(公告)号：US20050059252A1
公开(公告)日：2005-03-17
申请号：US10663471
申请日：2003-09-15
申请人： Omer Dokumaci , Bruce Doris , Kathryn Guarini , Suryanarayan Hegde , MeiKei Ieong , Erin Jones
发明人： Omer Dokumaci , Bruce Doris , Kathryn Guarini , Suryanarayan Hegde , MeiKei Ieong , Erin Jones
IPC分类号： H01L20060101 , H01L21/033 , H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L29/423 , H01L29/786
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.
摘要翻译：双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

62. 发明申请

US20050040460A1 Stress inducing spacers 有权
标题翻译：应力诱导垫片
公开(公告)号：US20050040460A1
公开(公告)日：2005-02-24
申请号：US10935136
申请日：2004-09-07
申请人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman , Xavier Baie
发明人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman , Xavier Baie
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/808 , H03B1/00 , H01L29/76 , H03K3/00
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

63. 发明申请

US20050014314A1 Ultra-thin channel device with raised source and drain and solid source extension doping 有权
标题翻译：超薄通道器件具有源极和漏极以及固态源极延迟掺杂
公开(公告)号：US20050014314A1
公开(公告)日：2005-01-20
申请号：US10916814
申请日：2004-08-12
申请人： Omer Dokumaci , Bruce Doris
发明人： Omer Dokumaci , Bruce Doris
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , H01L21/2255 , H01L29/6656 , H01L29/78621
摘要： The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.
摘要翻译：用于形成薄沟道MOSFET的本发明的方法包括：提供至少包括在绝缘层顶部具有半导体材料层的衬底和形成在半导体材料层顶上的栅极区域的结构的结构; 在结构顶部形成保形氧化膜; 植入保形氧化膜; 在所述共形氧化物膜的上方形成一组间隔物，所述一组侧壁间隔物邻近所述栅极区; 去除未被所述一组间隔物保护的氧化膜的部分以暴露所述半导体材料的区域; 在所述半导体材料的暴露区域上形成凸起的源极/漏极区域; 用第二掺杂杂质注入凸起的源/漏区以形成第二掺杂杂质区; 并退火最终结构以提供薄沟道MOSFET。

64. 发明授权

US08652898B2 Integrated circuit with a thin body field effect transistor and capacitor 失效
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08652898B2
公开(公告)日：2014-02-18
申请号：US13614908
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/77
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
摘要翻译：隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。在晶体管区域的第一半导体层上形成虚拟栅极结构。在第一半导体层上形成第二半导体层。第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。在形成电介质层之后，去除伪栅极结构形成第一腔。位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。

65. 发明授权

US08575698B2 MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
标题翻译：具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源
公开(公告)号：US08575698B2
公开(公告)日：2013-11-05
申请号：US13283308
申请日：2011-10-27
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译：场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

66. 发明授权

US08338260B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08338260B2
公开(公告)日：2012-12-25
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

67. 发明申请

US20120261754A1 MOSFET with Recessed channel FILM and Abrupt Junctions 有权
标题翻译：具有嵌入式通道FILM和突发接合的MOSFET
公开(公告)号：US20120261754A1
公开(公告)日：2012-10-18
申请号：US13086459
申请日：2011-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0603 , H01L29/1054 , H01L29/4236 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
摘要翻译：公开了用于制造具有凹陷沟道和突然结的MOSFET的MOSFET和方法。该方法包括在虚拟门就位的情况下创建源极和漏极扩展。源极/漏极延伸部分产生与硅衬底的扩散结。该方法通过去除伪栅极并蚀刻硅衬底中的凹槽来继续。凹部与源极和漏极结的至少一部分相交。然后，通过生长硅膜以至少部分地填充凹部而形成通道。该通道与源极和漏极具有尖锐的结，而沟道下方的未蚀刻的硅具有与源极和漏极的扩散结。因此，可以产生在相同晶体管中具有两个结区的尖锐和扩散的MOSFET。

68. 发明申请

US20080096330A1 HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 失效
标题翻译：高性能CMOS SOI器件在混合晶体导向衬底上的应用
公开(公告)号：US20080096330A1
公开(公告)日：2008-04-24
申请号：US11958877
申请日：2007-12-18
申请人： Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey Sleight , Min Yang
发明人： Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey Sleight , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

69. 发明申请

US20080070366A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 失效
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20080070366A1
公开(公告)日：2008-03-20
申请号：US11928787
申请日：2007-10-30
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

70. 发明申请

US20080064197A1 STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 有权
标题翻译：用于制造SiGe和/或Si：C的栅极应力工程的散装硅和SOI MOS器件中的分离自由应力通道的结构和方法
公开(公告)号：US20080064197A1
公开(公告)日：2008-03-13
申请号：US11931387
申请日：2007-10-31
申请人： Huilong Zhu , Bruce Doris , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Huajie Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/7845 , H01L21/28035 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/4925 , H01L29/66545 , H01L29/7842
摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.
摘要翻译：公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

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