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1. 发明申请

US20050040460A1 Stress inducing spacers 有权
标题翻译：应力诱导垫片
公开(公告)号：US20050040460A1
公开(公告)日：2005-02-24
申请号：US10935136
申请日：2004-09-07
申请人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman , Xavier Baie
发明人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman , Xavier Baie
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/808 , H03B1/00 , H01L29/76 , H03K3/00
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

2. 发明申请

US20050280051A1 Isolation structures for imposing stress patterns 审中-公开
公开(公告)号：US20050280051A1
公开(公告)日：2005-12-22
申请号：US11200958
申请日：2005-08-10
申请人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman
发明人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

3. 发明申请

US20060057787A1 Strained finfet cmos device structures 有权
标题翻译：应变finfet cmos设备结构
公开(公告)号：US20060057787A1
公开(公告)日：2006-03-16
申请号：US10536483
申请日：2002-11-25
申请人： Bruce Doris , Dureseti Chidambarrao , Meikei Leong , Jack Mandelman
发明人： Bruce Doris , Dureseti Chidambarrao , Meikei Leong , Jack Mandelman
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/7843 , H01L29/785
摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.
摘要翻译：半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9，所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

4. 发明申请

US20070069300A1 PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN 审中-公开
标题翻译：具有嵌入式源/漏极的平面超薄半导体绝缘体通道MOSFET
公开(公告)号：US20070069300A1
公开(公告)日：2007-03-29
申请号：US11162959
申请日：2005-09-29
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/2652 , H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

5. 发明申请

US20080040697A1 Design Structure Incorporating Semiconductor Device Structures with Voids 审中-公开
标题翻译：具有空隙的半导体器件结构的设计结构
公开(公告)号：US20080040697A1
公开(公告)日：2008-02-14
申请号：US11875986
申请日：2007-10-22
申请人： Dureseti Chidambarrao , Ricardo Donaton , Jack Mandelman
发明人： Dureseti Chidambarrao , Ricardo Donaton , Jack Mandelman
IPC分类号： G06F17/50
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823864 , H01L29/4991 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a gate electrode of a device, such as a field effect transistor, having an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer.
摘要翻译：用于设计，制造或测试设计的机器可读介质中的设备结构。该设计结构包括诸如场效应晶体管的器件的栅电极，其具有邻近栅电极的侧壁设置的气隙或空隙。空隙可以由靠近栅电极的侧壁的电介质隔离物和与电介质间隔物具有间隔关系的电介质层界定。

6. 发明授权

US06724031B1 Method for preventing strap-to-strap punch through in vertical DRAMs 有权
标题翻译：用于防止在垂直DRAM中穿带穿过的方法
公开(公告)号：US06724031B1
公开(公告)日：2004-04-20
申请号：US10340999
申请日：2003-01-13
申请人： Hiroyuki Akatsu , Dureseti Chidambarrao , Ramachandra Divakaruni , Jack Mandelman , Carl J. Radens
发明人： Hiroyuki Akatsu , Dureseti Chidambarrao , Ramachandra Divakaruni , Jack Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.
摘要翻译：一种动态随机存取存储单元，包括：形成在硅衬底中的沟槽电容器; 在所述沟槽电容器上方的硅衬底中形成的垂直MOSFET，所述垂直MOSFET具有栅极电极，从所述硅衬底的表面延伸到所述硅衬底的第一源极/漏极区域，与所述第二源极/漏极区域电接触的第二源极/ 沟槽电容器，形成在第一源极/漏极区域和埋入的第二源极/漏极区域之间的硅衬底中的沟道区域和设置在栅极电极和沟道区域之间的栅极氧化物层; 第一源极/漏极区域也属于相邻的垂直MOSFET，相邻的垂直MOSFET具有电连接到相邻沟槽电容器的掩埋的第三源极/漏极区域，所述埋入的第二和第三源极/漏极区域彼此延伸; 以及设置在埋入的第二和第三源极/漏极区之间的穿通防止区域。

7. 发明申请

US20060289909A1 Self-aligned low-k gate cap 失效
标题翻译：自对准低k门帽
公开(公告)号：US20060289909A1
公开(公告)日：2006-12-28
申请号：US11514605
申请日：2006-09-01
申请人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
发明人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
IPC分类号： H01L29/76
CPC分类号： H01L21/76834 , H01L21/28052 , H01L21/76897 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.
摘要翻译：提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。本发明的CMOS结构包括至少一个栅极区域，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

8. 发明申请

US20060099783A1 SELF-ALIGNED LOW-k GATE CAP 有权
标题翻译：自对准低k门槛
公开(公告)号：US20060099783A1
公开(公告)日：2006-05-11
申请号：US10904391
申请日：2004-11-08
申请人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
发明人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
IPC分类号： H01L21/3205
CPC分类号： H01L21/76834 , H01L21/28052 , H01L21/76897 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located atop a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.
摘要翻译：提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面上方的栅极导体; 以及与栅极导体自对准的低k电介质材料。

9. 发明申请

US20080064162A1 VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME 失效
标题翻译：垂直SOI晶体管存储单元及其形成方法
公开(公告)号：US20080064162A1
公开(公告)日：2008-03-13
申请号：US11931238
申请日：2007-10-31
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10841 , H01L27/10864
摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
摘要翻译：本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

10. 发明申请

US20080052659A1 Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore 失效
标题翻译：电可编程的pi形保险丝结构和设计过程
公开(公告)号：US20080052659A1
公开(公告)日：2008-02-28
申请号：US11923833
申请日：2007-10-25
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

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