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61. 发明授权

US5820486A Golf ball 失效
标题翻译：高尔夫球
公开(公告)号：US5820486A
公开(公告)日：1998-10-13
申请号：US687198
申请日：1996-07-25
申请人： Hiroaki Tanaka , Keiji Moriyama
发明人： Hiroaki Tanaka , Keiji Moriyama
IPC分类号： A63B37/00 , A63B37/12
CPC分类号： A63B37/12 , A63B37/0003 , A63B37/0031 , A63B37/0033 , A63B37/0037 , A63B37/0075 , Y10S273/06
摘要： A solid golf ball having a good shot feel and controllability as well as an excellent flight performance and durability which comprises a core and a cover covering the core, wherein the cover has a two layer structure composed of an outer cover and an inner cover, wherein the inner cover is prepared from a resin composition having a flexural modulus of 5,000 to 12,000 Kgf/cm.sup.2 and comprising a polyamide resin having a flexural modulus of 6,000 to 30,000 Kgf/cm.sup.2 with a thermoplastic elastomer having a JIS/A hardness of 30 to 98, in a weight ratio of polyamide: thermoplastic elastomer within the range of 95:5 to 50:50.
摘要翻译：具有良好的射击感和可控性的固体高尔夫球以及优异的飞行性能和耐久性，其包括芯和覆盖芯的盖，其中所述盖具有由外盖和内盖组成的两层结构，其中内盖由弯曲弹性模量为5000〜12,000Kgf / cm 2的树脂组合物制成，并且具有挠度为6,000〜30,000Kgf / cm 2的聚酰胺树脂，其热塑性弹性体的JIS / A硬度为30〜98 ，聚酰胺：热塑性弹性体的重量比在95:5至50:50的范围内。

62. 发明授权

US5812022A Differential amplifier circuit having low noise input transistors 失效
标题翻译：差分放大电路具有低噪声输入晶体管
公开(公告)号：US5812022A
公开(公告)日：1998-09-22
申请号：US715610
申请日：1996-09-18
申请人： Tetsuo Hirano , Ryuichirou Abe , Hiroaki Tanaka
发明人： Tetsuo Hirano , Ryuichirou Abe , Hiroaki Tanaka
IPC分类号： H03F1/26 , H03F3/45
CPC分类号： H03F3/45076
摘要： A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.
摘要翻译：在不增加成本的情况下，在CMOS运算放大器中使用噪声降低的差分放大器电路包括差分输入级电路，其中负载晶体管的栅极长度和差分输入晶体管的栅极长度被设置为使最小化内部晶体管噪声的最佳比率组件。

63. 发明授权

US5771376A Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit 失效
标题翻译：具有时钟控制功能的管道算术和逻辑系统，用于选择性地为给定单元提供时钟
公开(公告)号：US5771376A
公开(公告)日：1998-06-23
申请号：US725495
申请日：1996-10-04
申请人： Hiroshi Hayakawa , Harutsugu Fukumoto , Hiroaki Tanaka
发明人： Hiroshi Hayakawa , Harutsugu Fukumoto , Hiroaki Tanaka
IPC分类号： G06F9/312 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/325 , G06F9/3867 , G06F9/3869
摘要： A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.
摘要翻译：一种管道算术和逻辑系统，其能够在不使用NOP指令的情况下调整阶段之间的操作定时，从而提供其控制部分的尺寸减小。该系统具有解码器组，其包括被分成用于控制算术部分单元的解码器组，寄存器文件单元和程序计数器单元的解码器组，以及用于控制地址单元的解码器，还包括由地址单元控制解码器。来自外部源的时钟信号直接馈送到地址单元，同时通过时钟控制单元馈送到其它单元。当获取数据传输指令并重复执行MA阶段两次时，系统在执行第一MA级停止时钟控制单元以禁止地址单元以外的单元的操作。

64. 发明授权

US5727131A Neural network learning device 失效
标题翻译：神经网络学习装置
公开(公告)号：US5727131A
公开(公告)日：1998-03-10
申请号：US139710
申请日：1993-10-22
申请人： Joji Nakamura , Hiroaki Tanaka , Tomohisa Yoshimi , Takayoshi Kawai , Yuji Ito , Yuji Takeo
发明人： Joji Nakamura , Hiroaki Tanaka , Tomohisa Yoshimi , Takayoshi Kawai , Yuji Ito , Yuji Takeo
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/08 , G06N99/00 , G06E1/00 , G06E3/00
CPC分类号： G06N3/0454 , G06N3/08
摘要： A learning device that affects only the input-output relationships that should be additionally learned. A learning NN unit 8 capable of executing additional learning is provided separately from a learned NN unit 4 which is a basic control unit. The learned NN unit 4 produces a basic output in response to an input signal from a signal input unit 14, the learning NN unit 8 produces a correction amount desired by an individual person, and a desired control is performed based on the total value. When the output is changed, a difference is calculated between the changed output value and the basic output value from a first output unit 15, and the learning NN unit 8 executes the additional learning based upon the difference and the input value at this moment in compliance with a back-propagation method.
摘要翻译：仅影响应该额外学习的输入 - 输出关系的学习设备。与作为基本控制单元的学习NN单元4分开提供能够执行附加学习的学习NN单元8。所学习的NN单元4响应于来自信号输入单元14的输入信号产生基本输出，学习NN单元8产生个人期望的校正量，并且基于总值执行期望的控制。当输出改变时，在改变的输出值和来自第一输出单元15的基本输出值之间计算差值，并且学习NN单元8基于此时的差异和输入值执行附加学习具有反向传播方法。

65. 发明授权

US5717364A Mixer 失效
标题翻译：混合器
公开(公告)号：US5717364A
公开(公告)日：1998-02-10
申请号：US734468
申请日：1996-10-17
申请人： Mitsuo Ariie , Hiroaki Tanaka
发明人： Mitsuo Ariie , Hiroaki Tanaka
IPC分类号： H03D7/12 , H03D7/14 , H03B21/00 , H03C3/00 , H04B1/28
CPC分类号： H03D7/1441 , H03D7/125 , H03D7/1458 , H03D2200/0043 , H03D2200/0088 , H03D7/14
摘要： A small and inexpensive mixer that does not require a choke inductor and a large-capacitance capacitor. The mixer has a FET. The FET's source is grounded via a capacitor and is also connected to a power-supply terminal. The FET's gate is coupled to a bias voltage and also connected to a gate input terminal via a capacitor. The FET's drain is connected to an output terminal via a capacitor. A modulating signal is input into the power-supply terminal, and a local signal is input into the gate input terminal, so that a modulated signal is output from the output terminal.
摘要翻译：一种不需要扼流圈电感器和大容量电容器的小型廉价混频器。混频器有一个FET。 FET的源极通过电容器接地，并且还连接到电源端子。 FET的栅极耦合到偏置电压，并且还经由电容器连接到栅极输入端子。 FET的漏极通过电容器连接到输出端子。调制信号被输入到电源端子中，并且本地信号被输入到栅极输入端子中，从而从输出端子输出调制信号。

66. 发明授权

US5422854A Sense amplifier for receiving read outputs from a semiconductor memory array 失效
标题翻译：用于从半导体存储器阵列接收读出输出的读出放大器
公开(公告)号：US5422854A
公开(公告)日：1995-06-06
申请号：US104912
申请日：1993-08-12
申请人： Tetsuo Hirano , Takahiro Yanagi , Hiroaki Tanaka
发明人： Tetsuo Hirano , Takahiro Yanagi , Hiroaki Tanaka
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , H01L27/10 , G11C7/00
CPC分类号： G11C16/28
摘要： Output signals, representing data read out from a memory cell array comprising a plurality of memory cells arranged in a matrix of m rows and n columns, each cell comprising an EPROM transistor, are fed to a sense amplifier. A row of the memory cell array is selected by signals SRl-SRm coming from a row decoder. The output of the selected row is taken out by a column select transistor selected by signals SCl-SCn from a column decoder before being fed to the sense amplifier. The sense amplifier comprises a memory cell output detecting circuit having a first load transistor for receiving output read out from the memory cell array and a dummy cell output detecting circuit having a second load transistor to which dummy cell equivalent to the memory cell is connected. The circuit of the first load transistor and that of the second load transistor form a current mirror circuit. The sense amplifier also comprises a sense amplifier output evaluation circuit having differential amplifiers which transmit output voltages of the memory cell output detecting circuit and of the dummy cell output detecting circuit to reflect the respective currents running through the first and second load transistors.
摘要翻译：输出信号，表示从包括以m行和n列的矩阵排列的多个存储单元的存储单元阵列读出的数据，每个单元包括EPROM晶体管，被馈送到读出放大器。存储单元阵列的一行由来自行解码器的信号SR1-SRm选择。所选行的输出在被馈送到读出放大器之前由列解码器由信号SCl-SCn选择的列选择晶体管取出。读出放大器包括：存储单元输出检测电路，具有用于接收从存储单元阵列读出的输出的第一负载晶体管;以及具有第二负载晶体管的虚设单元输出检测电路，虚拟单元与该存储单元相连。第一负载晶体管和第二负载晶体管的电路形成电流镜电路。读出放大器还包括具有差分放大器的读出放大器输出评估电路，差分放大器传输存储单元输出检测电路和虚拟单元输出检测电路的输出电压，以反映通过第一和第二负载晶体管流过的相应电流。

67. 发明授权

US5357193A Semiconductor memory having a voltage stress applying circuit 失效
标题翻译：具有电压应力施加电路的半导体存储器
公开(公告)号：US5357193A
公开(公告)日：1994-10-18
申请号：US813523
申请日：1991-12-26
申请人： Hiroaki Tanaka , Masaru Koyanagi
发明人： Hiroaki Tanaka , Masaru Koyanagi
IPC分类号： G01R31/26 , G01R31/28 , G01R31/30 , G01R31/3161 , G01R31/317 , G01R31/3185 , G11C11/401 , G11C11/4094 , G11C29/06 , G11C29/50 , H01L21/66 , G11C7/00
CPC分类号： G01R31/3161 , G01R31/2884 , G01R31/30 , G01R31/31712 , G01R31/31715 , G11C11/4094 , G11C29/50 , G11C11/401
摘要： An semiconductor device includes an integrated circuit having first and second circuit sections formed on a semiconductor chip, at least one voltage stress testing pad formed on the semiconductor chip for supplying a voltage stress testing voltage or signal to the first circuit section, and a control circuit formed on the semiconductor chip for controlling and setting the second circuit section into a state corresponding to a voltage stress testing mode by using an input from the voltage stress testing pads.
摘要翻译：半导体器件包括具有形成在半导体芯片上的第一和第二电路部分的集成电路，形成在半导体芯片上的用于向第一电路部分提供电压应力测试电压或信号的至少一个电压应力测试焊盘，以及控制电路形成在半导体芯片上，用于通过使用来自电压应力测试垫的输入来将第二电路部分控制和设置成对应于电压应力测试模式的状态。

68. 发明授权

US5279995A Zirconia ceramics 失效
标题翻译：氧化锆陶瓷
公开(公告)号：US5279995A
公开(公告)日：1994-01-18
申请号：US38051
申请日：1993-03-25
申请人： Hiroaki Tanaka , Yutaka Kimura , Masamichi Obitsu
发明人： Hiroaki Tanaka , Yutaka Kimura , Masamichi Obitsu
IPC分类号： C04B35/486 , C04B35/48
CPC分类号： C04B35/486
摘要： A zirconia ceramic composed of crystals which scarcely undergo phase transformation from tetragonal system to monoclinic in the temperature range of from 100.degree. C. to 300.degree. C. even in the presence of water vapor or water is disclosed, said zirconia ceramic comprising at least 93% by weight of partially stabilized zirconia mainly composed of tetragonal crystals and containing mainly Y.sub.2 O.sub.3 and ZrO.sub.2 at the former to the latter molar ratio of from 2/98 to 4.5/95.5 and balance of at least one of the oxides selected from the group consisting of boron oxide, germanium oxide, and gallium oxide, wherein the content of the boron oxide is 1% by weight or less.
摘要翻译：公开了一种由晶体组成的氧化锆陶瓷，即使在水蒸汽或水的存在下也几乎不会在从100度到300度的温度范围内从四方晶相转变为单斜晶系，所述氧化锆陶瓷包含至少93 主要由四方晶体组成并且主要含有Y 2 O 3和ZrO 2的部分稳定化的氧化锆的重量百分数，其中后者的摩尔比为2/98至4.5 / 95.5，余量为至少一种选自以下的氧化物：氧化硼，氧化锗和氧化镓，其中氧化硼的含量为1重量％以下。

69. 发明授权

US5264808A Substrate potential adjusting apparatus 失效
标题翻译：基板电位调节装置
公开(公告)号：US5264808A
公开(公告)日：1993-11-23
申请号：US841535
申请日：1992-02-26
申请人： Hiroaki Tanaka
发明人： Hiroaki Tanaka
IPC分类号： G11C11/413 , G05F3/20 , G11C11/403 , G11C11/408 , H03K3/03 , H03B5/24 , H03K3/01
CPC分类号： G05F3/205 , H03K3/0315
摘要： A substrate potential adjusting apparatus of the invention includes: a pump circuit for drawing a current from a semiconductor substrate to adjust a substrate potential; ring oscillators for supplying a periodical signal to the pump circuit and causing the pump circuit to operate; a limiter circuit for detecting a potential of the semiconductor substrate and controlling to switch between operation and non-operation of the ring oscillators in accordance with the detected potential; and a selector circuit for changing the oscillation period of the periodical signal outputted from the ring oscillators in accordance with a signal inputted externally from a chip, the signal determining an operation mode of a circuit formed on the semiconductor substrate.
摘要翻译：本发明的衬底电位调节装置包括：泵电路，用于从半导体衬底吸取电流以调整衬底电位; 环形振荡器，用于向泵电路提供周期性信号并使泵电路工作; 限制电路，用于根据检测到的电位检测半导体衬底的电位并控制环形振荡器的工作和非操作之间的切换; 以及选择器电路，用于根据从芯片外部输入的信号来改变从环形振荡器输出的周期信号的振荡周期，该信号确定形成在半导体衬底上的电路的操作模式。

70. 发明授权

US5225753A Electric control apparatus for four-wheel steering system 失效
标题翻译：四轮转向系统电控装置
公开(公告)号：US5225753A
公开(公告)日：1993-07-06
申请号：US736977
申请日：1991-07-29
申请人： Shin Koike , Osamu Takeda , Hiroaki Tanaka , Mizuho Sugiyama , Kaoru Ohashi , Hitoshi Iwata , Masaru Ishikawa
发明人： Shin Koike , Osamu Takeda , Hiroaki Tanaka , Mizuho Sugiyama , Kaoru Ohashi , Hitoshi Iwata , Masaru Ishikawa
IPC分类号： B62D6/00 , B62D5/04 , B62D7/14 , B62D7/15 , B62D101/00 , B62D113/00 , B62D133/00 , B62D137/00
CPC分类号： B62D7/1581 , B62D7/159
摘要： In an electric control apparatus for a four-wheel steering system including an electric motor the rotary angle of which is electrically controlled in accordance with a target steering angle of rear road wheels, and a hydro-mechanical tracer mechanism having a fluid control valve the valve element of which is drivingly connected to the electric motor to be displaced in proportion to the rotary angle of the electric motor, the tracer mechanism being arranged to steer the rear road wheels in proportion to a displacement amount of the valve element, the target steering angle is converted into a control value for rotation of the electric motor, and a drive signal indicative of the control value is applied to the electric motor. The electric control apparatus is designed to greatly change the control value to and from zero when the target steering angle is less than a predetermined small angle and to change the control value in proportion to the target steering angle when the target steering angle is more than the predetermined small angle.

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