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61. 发明申请

US20070018218A1 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell 审中-公开
标题翻译：鳍场效应晶体管存储单元，鳍场效应晶体管存储单元的布置及制造鳍场效应晶体管存储单元的方法
公开(公告)号：US20070018218A1
公开(公告)日：2007-01-25
申请号：US11455907
申请日：2006-06-19
申请人： Johannes Kretz , Franz Kreupl , Michael Specht , Gernot Steinlesberger
发明人： Johannes Kretz , Franz Kreupl , Michael Specht , Gernot Steinlesberger
IPC分类号： H01L29/94
CPC分类号： H01L29/7923 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/66833 , H01L29/785
摘要： The invention relates to a bridge field-effect transistor storage cell comprising first and second source/drain areas and a channel area arranged therebetween, which are formed in a semiconductor bridge. The inventive storage cell also comprises a charge-coupled layer that is disposed at least partially on the semiconductor bridge and a metal conductive gate area on at least one part of the charge-coupled layer that is arranged in such a way that electric charge carriers are selectively introducible or removable by applying a predetermined electric voltage to the bridge field-effect transistor storage cell.
摘要翻译：本发明涉及一种桥式场效应晶体管存储单元，其包括形成在半导体桥中的第一和第二源极/漏极区域和布置在其间的沟道区域。本发明的存储单元还包括至少部分地设置在半导体电桥上的电荷耦合层和电荷耦合层的至少一部分上的金属导电栅极区域，其中电荷载体为通过向桥式场效应晶体管存储单元施加预定的电压来选择性地引入或去除。

62. 发明申请

US20060234080A1 Integrated electronic component 有权
标题翻译：集成电子元件
公开(公告)号：US20060234080A1
公开(公告)日：2006-10-19
申请号：US11211168
申请日：2005-08-23
申请人： Robert Seidel , Franz Kreupl , Andrew Graham
发明人： Robert Seidel , Franz Kreupl , Andrew Graham
IPC分类号： C03C27/00 , B32B15/04 , B32B9/00
CPC分类号： H01L21/76876 , B82Y10/00 , H01L21/76802 , H01L21/76879 , H01L23/5226 , H01L23/53276 , H01L2221/1078 , H01L2221/1094 , H01L2924/0002 , Y10T428/12535 , Y10T428/12576 , Y10T428/12611 , Y10T428/24917 , Y10T428/30 , H01L2924/00
摘要： An integrated electronic component having a substrate, a metal multilayer system, which is arranged at least on regions of the substrate, and a nonconductive layer, which is arranged on the metal multilayer system and has at least one contact hole, in which at least one carbon nanotube is grown on the metal multilayer system at the bottom of the contact hole. The metal multilayer system includes a high-melting metal layer, a metal separating layer, a catalyst layer, and a final metal separating layer. The high-melting metal layer is composed of at least one of tantalum, molybdenum, and tungsten. The metal separating layer is composed of aluminum, gold, or silver. The catalyst layer is composed of at least one of iron, cobalt, nickel, yttrium, titanium, platinum, and palladium, and a combination thereof. The final metal separating layer, which is arranged above the catalyst layer, is composed of aluminum.
摘要翻译：一种集成电子部件，其具有基板，至少布置在所述基板的区域上的金属多层系统和非导电层，所述非导电层布置在所述金属多层系统上并且具有至少一个接触孔，其中至少一个碳纳米管在接触孔底部的金属多层体系上生长。金属多层体系包括高熔点金属层，金属分离层，催化剂层和最终金属分离层。高熔点金属层由钽，钼和钨中的至少一种构成。金属分离层由铝，金或银构成。催化剂层由铁，钴，镍，钇，钛，铂和钯中的至少一种及其组合构成。设置在催化剂层上方的最终金属分离层由铝构成。

63. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

64. 发明授权

US08737111B2 Memory cell with resistance-switching layers 有权
标题翻译：具有电阻切换层的存储单元
公开(公告)号：US08737111B2
公开(公告)日：2014-05-27
申请号：US13157191
申请日：2011-06-09
申请人： Franz Kreupl , Xiying Costa , James Kai , Raghuveer S. Makala
发明人： Franz Kreupl , Xiying Costa , James Kai , Raghuveer S. Makala
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

65. 发明授权

US08487292B2 Resistance-switching memory cell with heavily doped metal oxide layer 有权
标题翻译：具有重掺杂金属氧化物层的电阻切换存储单元
公开(公告)号：US08487292B2
公开(公告)日：2013-07-16
申请号：US12842798
申请日：2010-07-23
申请人： Deepak C. Sekar , Franz Kreupl
发明人： Deepak C. Sekar , Franz Kreupl
IPC分类号： H01L47/00
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1641 , H01L45/1675
摘要： A non-volatile resistance-switching memory element includes a resistance-switching element formed from a metal oxide layer having a dopant which is provided at a relatively high concentration such as 10% or greater. Further, the dopant is a cation having a relatively large ionic radius such as 70 picometers or greater, such as Magnesium, Chromium, Calcium, Scandium or Yttrium. A cubic fluorite phase lattice may be formed in the metal oxide even at room temperature so that switching power may be reduced. The memory element may be pillar-shaped, extending between first and second electrodes and being in series with a steering element such as a diode. The metal oxide layer may be deposited at the same time as the dopant. Or, using atomic layer deposition, an oxide of a first metal can be deposited, followed by an oxide of a second metal, followed by annealing to cause intermixing, in repeated cycles.
摘要翻译：非易失性电阻切换存储元件包括由具有以比较高的浓度（例如10％以上）设置的掺杂剂的金属氧化物层形成的电阻切换元件。此外，掺杂剂是诸如镁，铬，钙，钪或钇之类的诸如70皮度或更大的离子半径相对较大的阳离子。即使在室温下也可以在金属氧化物中形成立方萤石相晶格，从而可以降低开关功率。存储元件可以是柱形的，在第一和第二电极之间延伸并且与诸如二极管的转向元件串联。金属氧化物层可以与掺杂剂同时沉积。或者，使用原子层沉积，可沉积第一金属的氧化物，然后沉积第二金属的氧化物，然后在重复循环中进行退火以引起混合。

66. 发明授权

US08435831B2 Non-volatile storage with metal oxide switching element and methods for fabricating the same 有权
公开(公告)号：US08435831B2
公开(公告)日：2013-05-07
申请号：US12942575
申请日：2010-11-09
申请人： Deepak C. Sekar , Franz Kreupl , Raghuveer Makala , Peter Rabkin
发明人： Deepak C. Sekar , Franz Kreupl , Raghuveer Makala , Peter Rabkin
IPC分类号： H01L21/00
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1641 , H01L45/1675
摘要： Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide.

67. 发明授权

US08395926B2 Memory cell with resistance-switching layers and lateral arrangement 有权
标题翻译：具有电阻切换层和横向布置的存储单元
公开(公告)号：US08395926B2
公开(公告)日：2013-03-12
申请号：US13157200
申请日：2011-06-09
申请人： Franz Kreupl , Ritu Shrivastava
发明人： Franz Kreupl , Ritu Shrivastava
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME). The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The layers can be provided in a lateral arrangement, such as an end-to-end, face-to-face, L-shaped or U-shaped arrangement. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。这些层可以以诸如端对端，面对面，L形或U形布置的横向布置来设置。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。

68. 发明授权

US08298932B2 Vertical interconnect structure, memory device and associated production method 有权
公开(公告)号：US08298932B2
公开(公告)日：2012-10-30
申请号：US13167744
申请日：2011-06-24
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L21/4763
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

69. 发明授权

US08216639B2 Methods for elimination or reduction of oxide and/or soot deposition in carbon containing layers 有权
标题翻译：消除或减少含碳层中氧化物和/或烟灰沉积的方法
公开(公告)号：US08216639B2
公开(公告)日：2012-07-10
申请号：US11303639
申请日：2005-12-16
申请人： Maik Liebau , Franz Kreupl , Georg Duesberg , Eugen Unger
发明人： Maik Liebau , Franz Kreupl , Georg Duesberg , Eugen Unger
IPC分类号： C23C16/00
CPC分类号： C23C16/0227 , C23C16/26
摘要： One embodiment of the present invention provides a method for the deposition of a Carbon containing layer on a Silicon surface wherein a (i) substantially Silicon-oxide-free or reduced oxide interface results between Silicon and the Carbon containing layer during the deposition. In another embodiment, the present invention provides a method for deposition of a Carbon containing layer wherein the deposition process is substantially soot (particle)-free or reduction of soot.
摘要翻译：本发明的一个实施方案提供了一种用于在硅表面上沉积含碳层的方法，其中在沉积期间在硅和含碳层之间产生（i）基本上不含氧化硅的氧化物或还原氧化物界面。在另一个实施方案中，本发明提供了一种用于沉积含碳层的方法，其中沉积过程基本上是烟灰（无颗粒）或烟灰的还原。

70. 发明申请

US20110310655A1 Composition Of Memory Cell With Resistance-Switching Layers 有权
标题翻译：具有电阻切换层的存储单元的组成
公开(公告)号：US20110310655A1
公开(公告)日：2011-12-22
申请号：US13157204
申请日：2011-06-09
申请人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
发明人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

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