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61. 发明申请

US20060175660A1 VERTICAL BODY-CONTACTED SOI TRANSISTOR 有权
标题翻译：垂直接触式SOI晶体管
公开(公告)号：US20060175660A1
公开(公告)日：2006-08-10
申请号：US10906238
申请日：2005-02-10
申请人： Kangguo Cheng , Gary Bronner , Ramachandra Divakaruni , Carl Radens
发明人： Kangguo Cheng , Gary Bronner , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译：提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

62. 发明申请

US20050247966A1 OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI 有权
标题翻译：在SOI上用于eDRAM的盒式垂直晶体管
公开(公告)号：US20050247966A1
公开(公告)日：2005-11-10
申请号：US10709450
申请日：2004-05-06
申请人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
发明人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L21/8242 , H01L27/108 , H01L31/119
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

63. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

64. 发明授权

US06420749B1 Trench field shield in trench isolation 失效
标题翻译：沟槽隔离屏蔽沟槽
公开(公告)号：US06420749B1
公开(公告)日：2002-07-16
申请号：US09602427
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/76232 , H01L21/76895 , H01L21/823475 , H01L27/10897
摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.
摘要翻译：一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间的沟槽的绝缘体。第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。第一装置可以独立于第二装置而被偏置。接触件在衬底的表面上方延伸。第一接触件邻接第一器件和第一导电侧壁间隔物。绝缘体将导电侧墙隔离开。第一接触件可以在第一导体和第二导体之间等距。导电侧壁间隔件包括场屏蔽。

65. 发明授权

US06265279B1 Method for fabricating a trench capacitor 失效
标题翻译：沟槽电容器的制造方法
公开(公告)号：US06265279B1
公开(公告)日：2001-07-24
申请号：US09404906
申请日：1999-09-24
申请人： Carl Radens , Jack A. Mandelman , Joachim Hoepfner
发明人： Carl Radens , Jack A. Mandelman , Joachim Hoepfner
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A trench capacitor, in accordance with the present invention, includes a trench formed in a substrate. The trench has a buried plate formed adjacent to a lower portion of the trench. A dielectric collar is formed along vertical sidewalls of the trench. A node diffusion region is formed adjacent to the trench for connecting to a storage node in the trench. A dopant region is formed laterally outward from the trench and adjacent to the collar, and the dopant region includes a profile having a lower portion extending further laterally outward from the trench than an upper portion of the profile wherein operation of a parasitic transistor formed adjacent to the trench between the node diffusion and the buried plate is disrupted by the dopant region. Methods for forming the dopant region are also disclosed and claimed.
摘要翻译：根据本发明的沟槽电容器包括形成在衬底中的沟槽。沟槽具有邻近沟槽下部形成的掩埋板。沿着沟槽的垂直侧壁形成介电环。在沟槽附近形成节点扩散区域，以连接到沟槽中的存储节点。掺杂剂区域从沟槽横向向外形成并且与套环相邻，并且掺杂剂区域包括轮廓，该轮廓具有比轮廓的上部更远离沟槽进一步横向向外延伸的轮廓，其中形成为邻近节点扩散和掩埋板之间的沟槽被掺杂剂区域破坏。还公开并要求保护形成掺杂剂区域的方法。

66. 发明授权

US6143599A Method for manufacturing memory cell with trench capacitor 有权
标题翻译：具有沟槽电容器的存储单元的制造方法
公开(公告)号：US6143599A
公开(公告)日：2000-11-07
申请号：US235621
申请日：1999-01-22
申请人： Byeong Y. Kim , Carl Radens , Jochen Beintner
发明人： Byeong Y. Kim , Carl Radens , Jochen Beintner
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A memory cell includes a transistor and a capacitor that is a doped polysilicon filled trench. A doped polycrystalline strap provides a low resistance connection between a source region of the transistor and the polysilicon fill and is shaped to overlie both a top surface and a side surface of the source region of the transistor.
摘要翻译：存储单元包括晶体管和作为掺杂多晶硅填充沟槽的电容器。掺杂的多晶带提供了晶体管的源极区域和多晶硅填充物之间的低电阻连接，并且被成形为覆盖晶体管的源极区域的顶表面和侧表面。

67. 发明授权

US08207028B2 Two-dimensional patterning employing self-assembled material 有权
标题翻译：采用自组装材料的二维图案
公开(公告)号：US08207028B2
公开(公告)日：2012-06-26
申请号：US12017598
申请日：2008-01-22
申请人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
发明人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.
摘要翻译：具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的第一纳米级自对准自组装嵌套线结构由第一层内的第一自组装嵌段共聚物形成。第一层填充有填充材料，并且第二层沉积在包含第一纳米级嵌套线结构的第一层之上。具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层内的第二自组装嵌段共聚物形成。第一纳米级嵌套线结构和第二纳米级嵌套线结构的复合图案被转移到第一层下面的底层中以形成在两个方向上包含周期性的结构阵列。

68. 发明授权

US07825420B2 Method for forming slot via bitline for MRAM devices 有权
标题翻译：用于通过MRAM器件的位线形成槽的方法
公开(公告)号：US07825420B2
公开(公告)日：2010-11-02
申请号：US12539942
申请日：2009-08-12
申请人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

69. 发明授权

US07635884B2 Method and structure for forming slot via bitline for MRAM devices 有权
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：US07635884B2
公开(公告)日：2009-12-22
申请号：US11193660
申请日：2005-07-29
申请人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

70. 发明申请

US20080261369A1 STRUCTURE AND METHOD FOR MOSFET WITH REDUCED EXTENSION RESISTANCE 有权
标题翻译：具有降低延伸电阻的MOSFET的结构和方法
公开(公告)号：US20080261369A1
公开(公告)日：2008-10-23
申请号：US12121922
申请日：2008-05-16
申请人： Dureseti Chidambarrao , Carl Radens
发明人： Dureseti Chidambarrao , Carl Radens
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6653 , H01L29/7833 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
摘要翻译：本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。本发明还提供了利用该方法形成的半导体结构。半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

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