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61. 发明授权

US06869895B1 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/255 , H01L21/02 , H01L21/66 , H01L21/31
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

62. 发明申请

US20070092990A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 失效
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：US20070092990A1
公开(公告)日：2007-04-26
申请号：US11163523
申请日：2005-10-21
申请人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
发明人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

63. 发明申请

US20060108651A1 Lowered Source/Drain Transistors 审中-公开
标题翻译：降低源/漏晶体管
公开(公告)号：US20060108651A1
公开(公告)日：2006-05-25
申请号：US10904660
申请日：2004-11-22
申请人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Oleg Gluschenkov , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Oleg Gluschenkov , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
IPC分类号： H01L29/94
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/0843 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure
摘要翻译：一种新颖的晶体管结构及其制造方法。新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。用于制造晶体管结构的方法从在半导体层顶部的平面半导体层和栅叠层开始。然后，去除栅极堆叠的相对侧上的半导体层的顶部区域。然后，去除区域下方的区域被掺杂以形成晶体管结构的降低的S / D区域

64. 发明申请

US20080042174A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 有权
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：US20080042174A1
公开(公告)日：2008-02-21
申请号：US11923075
申请日：2007-10-24
申请人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
发明人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

65. 发明申请

US20060124993A1 SIDEWALL SEMICONDUCTOR TRANSISTORS 有权
标题翻译：端子半导体晶体管
公开(公告)号：US20060124993A1
公开(公告)日：2006-06-15
申请号：US10905041
申请日：2004-12-13
申请人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1083 , H01L29/66795
摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.
摘要翻译：一种新颖的晶体管结构及其制造方法。晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面其基本上平行于衬底的顶表面。

66. 发明申请

US20050255386A1 METHODS AND STRUCTURES FOR PROTECTING ONE AREA WHILE PROCESSING ANOTHER AREA ON A CHIP 失效
标题翻译：在芯片上处理其他区域时保护一个区域的方法和结构
公开(公告)号：US20050255386A1
公开(公告)日：2005-11-17
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03C5/00 , G03F7/11 , G03F9/00 , H01L21/033 , H01L21/311 , H01L21/331
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

67. 发明申请

US20050180521A1 REDUNDANCY STRUCTURE AND METHOD FOR HIGH-SPEED SERIAL LINK 失效
标题翻译：用于高速串行链路的冗余结构和方法
公开(公告)号：US20050180521A1
公开(公告)日：2005-08-18
申请号：US10708240
申请日：2004-02-18
申请人： Louis Hsu , Carl Radens , Li-Kong Wang
发明人： Louis Hsu , Carl Radens , Li-Kong Wang
IPC分类号： H04L1/22 , H04L25/02 , H04L25/08 , H04L27/04
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译：提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。在一个优选形式中，连接元件包括保险丝和反熔丝。在另一种形式中，连接元件包括微机电（MEM）开关。连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

68. 发明申请

US20070007601A1 Vertical MOSFET SRAM cell 审中-公开
标题翻译：垂直MOSFET SRAM单元
公开(公告)号：US20070007601A1
公开(公告)日：2007-01-11
申请号：US11509866
申请日：2006-08-25
申请人： Louis Hsu , Oleg Gluschenkov , Jack Mandelman , Carl Radens
发明人： Louis Hsu , Oleg Gluschenkov , Jack Mandelman , Carl Radens
IPC分类号： H01L21/8244 , H01L29/94 , H01L29/76
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译：形成SRAM单元装置的方法包括以下步骤。形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到到共同的身体层。形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。然后，连接FET晶体管以形成SRAM单元。

69. 发明申请

US20050087814A1 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US20050087814A1
公开(公告)日：2005-04-28
申请号：US10995444
申请日：2004-11-23
申请人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
发明人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94 , H01L21/8238
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

70. 发明申请

US20060006166A1 On-chip power supply regulator and temperature control system 失效
标题翻译：片上电源调节器和温度控制系统
公开(公告)号：US20060006166A1
公开(公告)日：2006-01-12
申请号：US10884933
申请日：2004-07-06
申请人： Howard Chen , William Ferrante , Louis Hsu , Carl Radens
发明人： Howard Chen , William Ferrante , Louis Hsu , Carl Radens
IPC分类号： H05B1/02 , H05B3/00
CPC分类号： G05D23/20 , G05D23/1931 , Y10T307/469
摘要： An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.
摘要翻译：片上温度控制系统包括监测芯片温度的温度传感器和检查温度是否在可接受范围内的滞后比较器。如果温度超出范围，参考调节电路响应于迟滞比较器来调节片上电压以局部地调节局部电源电压来控制温度。

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