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61. 发明授权

US08614489B2 Vertical NPNP structure in a triple well CMOS process 有权
标题翻译：三阱CMOS工艺中的垂直NPNP结构
公开(公告)号：US08614489B2
公开(公告)日：2013-12-24
申请号：US13614072
申请日：2012-09-13
申请人： John B. Campi , Shunhua Thomas Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi , Shunhua Thomas Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/76
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

62. 发明授权

US08610249B2 Non-planar capacitor and method of forming the non-planar capacitor 有权
标题翻译：非平面电容器和非平面电容器的形成方法
公开(公告)号：US08610249B2
公开(公告)日：2013-12-17
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译：这里公开了非平面电容器的实施例。非平面电容器可以包括在半导体衬底上方的多个鳍片。每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。门结构可以穿过翅片的中心部分。该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。

63. 发明授权

US08586423B2 Silicon controlled rectifier with stress-enhanced adjustable trigger voltage 有权
公开(公告)号：US08586423B2
公开(公告)日：2013-11-19
申请号：US13168232
申请日：2011-06-24
申请人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
IPC分类号： H01L21/02
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

64. 发明授权

US08575718B2 Programmable electrical fuse 失效
标题翻译：可编程电气保险丝
公开(公告)号：US08575718B2
公开(公告)日：2013-11-05
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

65. 发明授权

US08445355B2 Metal-insulator-metal capacitors with high capacitance density 有权
标题翻译：具有高电容密度的金属 - 绝缘体 - 金属电容器
公开(公告)号：US08445355B2
公开(公告)日：2013-05-21
申请号：US12969004
申请日：2010-12-15
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/82 , H01L23/5223 , H01L27/0207 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.
摘要翻译：金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

66. 发明授权

US08421128B2 Semiconductor device heat dissipation structure 失效
标题翻译：半导体器件散热结构
公开(公告)号：US08421128B2
公开(公告)日：2013-04-16
申请号：US11960030
申请日：2007-12-19
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L23/62
CPC分类号： H01L23/34 , H01L21/743 , H01L21/76877 , H01L21/84 , H01L23/3677 , H01L27/0255 , H01L27/1203 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.
摘要翻译：半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。

67. 发明授权

US08377754B1 Stress enhanced junction engineering for latchup SCR 有权
标题翻译：应力增强连接工程用于闭锁SCR
公开(公告)号：US08377754B1
公开(公告)日：2013-02-19
申请号：US13269819
申请日：2011-10-10
申请人： John B. Campi, Jr. , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra
发明人： John B. Campi, Jr. , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra
IPC分类号： H01L21/332
CPC分类号： H01L29/66068 , H01L29/66393 , H01L29/7436
摘要： A method of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area; and removing the mask.
摘要翻译：一种形成包括闭锁硅可控整流器（SCR）的IC器件的方法包括在衬底的顶表面上形成掩模，其中所述掩模覆盖所述衬底的第一部分并且暴露所述衬底的位于在衬底上的n阱和p阱中的一个; 蚀刻所述基板的暴露的第二部分以形成蚀刻区域; 通过选择性外延沉积在蚀刻区域中形成闭锁SCR的应力工程结; 并取下面罩。

68. 发明授权

US08373267B2 Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure 有权
公开(公告)号：US08373267B2
公开(公告)日：2013-02-12
申请号：US13196404
申请日：2011-08-02
申请人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
IPC分类号： H01L29/66 , H01L23/62
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

69. 发明授权

US08242584B2 Structure and method to create stress trench 有权
标题翻译：构造应力沟的结构和方法
公开(公告)号：US08242584B2
公开(公告)日：2012-08-14
申请号：US12647796
申请日：2009-12-28
申请人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
发明人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
IPC分类号： H01L29/06
CPC分类号： H01L29/8086 , H01L21/76283 , H01L29/66901 , H01L29/7846
摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
摘要翻译：提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。还公开了相关方法。

70. 发明授权

US08084822B2 Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices 有权
标题翻译：增强的应力保持鳍式FET器件和制造增强的应力保持鳍式FET器件的方法
公开(公告)号：US08084822B2
公开(公告)日：2011-12-27
申请号：US12570384
申请日：2009-09-30
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed Hickory Rankin , Robert R. Robison , William Robert Tonti
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed Hickory Rankin , Robert R. Robison , William Robert Tonti
IPC分类号： H01L29/66
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.
摘要翻译： Fin-FET和制造鳍式FET的方法。所述方法包括：在半导体衬底的顶表面上提供包括氧化硅层的衬底，在氧化硅层的顶表面上的加强层和在加强层的顶表面上的单晶硅层; 从单晶硅层形成翅片; 在翅片的通道区域的翅片和相对侧上形成源极和漏极; 在所述沟道区域中的所述鳍片的至少一个表面上形成栅极电介质层; 以及在所述栅极电介质层上形成栅电极。

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