专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08354722B2 SCR/MOS clamp for ESD protection of integrated circuits 失效
标题翻译：用于集成电路ESD保护的SCR / MOS钳位
公开(公告)号：US08354722B2
公开(公告)日：2013-01-15
申请号：US13149174
申请日：2011-05-31
申请人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/78 , H01L29/788 , H02H9/00
CPC分类号： H01L29/742 , H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.
摘要翻译：静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。可以在p阱中形成NFET，并且可以在n阱中形成PFET。在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

2. 发明授权

US08377754B1 Stress enhanced junction engineering for latchup SCR 有权
标题翻译：应力增强连接工程用于闭锁SCR
公开(公告)号：US08377754B1
公开(公告)日：2013-02-19
申请号：US13269819
申请日：2011-10-10
申请人： John B. Campi, Jr. , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra
发明人： John B. Campi, Jr. , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra
IPC分类号： H01L21/332
CPC分类号： H01L29/66068 , H01L29/66393 , H01L29/7436
摘要： A method of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area; and removing the mask.
摘要翻译：一种形成包括闭锁硅可控整流器（SCR）的IC器件的方法包括在衬底的顶表面上形成掩模，其中所述掩模覆盖所述衬底的第一部分并且暴露所述衬底的位于在衬底上的n阱和p阱中的一个; 蚀刻所述基板的暴露的第二部分以形成蚀刻区域; 通过选择性外延沉积在蚀刻区域中形成闭锁SCR的应力工程结; 并取下面罩。

3. 发明授权

US08513738B2 ESD field-effect transistor and integrated diffusion resistor 有权
标题翻译： ESD场效应晶体管和集成扩散电阻
公开(公告)号：US08513738B2
公开(公告)日：2013-08-20
申请号：US13188094
申请日：2011-07-21
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/60
CPC分类号： H01L29/41775 , H01L27/0266 , H01L29/1087 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
摘要翻译：静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

4. 发明授权

US08299533B2 Vertical NPNP structure in a triple well CMOS process 有权
标题翻译：三阱CMOS工艺中的垂直NPNP结构
公开(公告)号：US08299533B2
公开(公告)日：2012-10-30
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/62
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

5. 发明授权

US08363367B2 Electrical overstress protection circuit 有权
标题翻译：电气过载保护电路
公开(公告)号：US08363367B2
公开(公告)日：2013-01-29
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译：提供了一种用于电力过应力（EOS）保护的半导体电路。半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

6. 发明授权

US08760827B2 Robust ESD protection circuit, method and design structure for tolerant and failsafe designs 有权
标题翻译：强大的ESD保护电路，容错和故障安全设计的方法和设计结构
公开(公告)号：US08760827B2
公开(公告)日：2014-06-24
申请号：US12424169
申请日：2009-04-15
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H3/22
CPC分类号： H01L27/0274 , H01L2924/0002 , H01L2924/00
摘要： A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.
摘要翻译：公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。电路包括在ESD事件期间关闭层叠的NFET静电放电（ESD）保护电路的顶部NFET的中间接点控制电路。

7. 发明授权

US08730624B2 Electrostatic discharge power clamp with a JFET based RC trigger circuit 有权
标题翻译：具有基于JFET的RC触发电路的静电放电电源钳位
公开(公告)号：US08730624B2
公开(公告)日：2014-05-20
申请号：US13076625
申请日：2011-03-31
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.
摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET）电阻器作为RC网络的电阻元件。

8. 发明授权

US08614489B2 Vertical NPNP structure in a triple well CMOS process 有权
标题翻译：三阱CMOS工艺中的垂直NPNP结构
公开(公告)号：US08614489B2
公开(公告)日：2013-12-24
申请号：US13614072
申请日：2012-09-13
申请人： John B. Campi , Shunhua Thomas Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi , Shunhua Thomas Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/76
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

9. 发明授权

US08634172B2 Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure 有权
标题翻译：基于集成JFET的可控硅整流器静电放电保护电路，工作方式和设计结构
公开(公告)号：US08634172B2
公开(公告)日：2014-01-21
申请号：US12782296
申请日：2010-05-18
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H01L27/0262
摘要： An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base.
摘要翻译：增强型导通时间基于SCR的静电放电（ESD）保护电路包括集成JFET，使用方法和设计结构。增强的导通时间硅可控整流（SCR）基静电放电（ESD）保护电路包括与NPN基极串联的集成JFET。

10. 发明授权

US08737028B2 RC-triggered ESD clamp device with feedback for time constant adjustment 有权
标题翻译： RC触发ESD钳位装置，具有时间常数调整反馈
公开(公告)号：US08737028B2
公开(公告)日：2014-05-27
申请号：US13312047
申请日：2011-12-06
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译：用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。场效应晶体管与反相器的输出端相连。响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式