专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20080162877A1 Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
标题翻译：具有共享内存的非均匀多处理器系统
公开(公告)号：US20080162877A1
公开(公告)日：2008-07-03
申请号：US12049324
申请日：2008-03-15
申请人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
发明人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： H04L63/168 , H04L67/10
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

62. 发明授权

US07389363B2 System and method for flexible multiple protocols 有权
标题翻译：灵活多协议的系统和方法
公开(公告)号：US07389363B2
公开(公告)日：2008-06-17
申请号：US11050022
申请日：2005-02-03
申请人： Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
摘要翻译：介绍了灵活多协议的系统和方法。可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。

63. 发明申请

US20080126817A1 METHOD AND APPARATUS FOR MANAGING THE POWER CONSUMPTION OF A DATA PROCESSING SYSTEM 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US20080126817A1
公开(公告)日：2008-05-29
申请号：US12025649
申请日：2008-02-04
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

64. 发明授权

US07356713B2 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US07356713B2
公开(公告)日：2008-04-08
申请号：US10631537
申请日：2003-07-31
申请人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
发明人： Shigehiro Asano , Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Alvan Wing Ng , Michael Fan Wang , Thuong Quang Truong
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops.
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式。

65. 发明授权

US07120748B2 Software-controlled cache set management 失效
标题翻译：软件控制缓存集管理
公开(公告)号：US07120748B2
公开(公告)日：2006-10-10
申请号：US10655367
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Roy Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Roy Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.
摘要翻译：本发明提供了一种用于管理高速缓存替换资格的系统。第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器缓存。范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格响应接收的L2标签替换控制标记。响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

66. 发明授权

US07062612B2 Updating remote locked cache 失效
标题翻译：更新远程锁定缓存
公开(公告)号：US07062612B2
公开(公告)日：2006-06-13
申请号：US10318594
申请日：2002-12-12
申请人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
发明人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry in the cache. Upon determining that the snoop request has a valid entry in the cache, the data is caught and sent to the cache for update.
摘要翻译：提供了一种用于直接访问数据缓存的系统和方法。数据传输请求被发送到系统总线，用于将数据传送到系统存储器。数据传输请求被窥探。侦听请求被发送到缓存。确定窥探请求是否在高速缓存中具有有效的条目。在确定窥探请求在缓存中具有有效条目时，数据被捕获并发送到缓存以供更新。

67. 发明授权

US06961820B2 System and method for identifying and accessing streaming data in a locked portion of a cache 失效
标题翻译：用于在高速缓存的锁定部分中识别和访问流数据的系统和方法
公开(公告)号：US06961820B2
公开(公告)日：2005-11-01
申请号：US10366440
申请日：2003-02-12
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David J. Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David J. Shippy , Thuong Quang Truong
IPC分类号： G06F12/08 , G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.
摘要翻译：提供了一种系统和方法，用于在计算机系统中用高速缓存高效地处理数据。计算机系统具有处理器，缓存和系统存储器。处理器发出流数据的数据请求。流数据具有一个或多个小数据部分。系统存储器与处理器通信。系统存储器具有用于存储流数据的特定区域。缓存耦合到处理器。高速缓存具有为流数据锁定的预定义区域。高速缓存控制器耦合到高速缓存，并且与处理器和系统存储器通信，以将流式数据的至少一个小数据部分从系统存储器的特定区域发送到高速缓存的预定义区域在缓存的预定义区域中没有找到小数据部分。

68. 发明授权

US06907477B2 Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors 失效
标题翻译：使用DMAC的对称多处理系统允许连接的处理器进行地址转换
公开(公告)号：US06907477B2
公开(公告)日：2005-06-14
申请号：US10782044
申请日：2004-02-19
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/28 , G06F9/28 , G06F13/368
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

69. 发明授权

US06820143B2 On-chip data transfer in multi-processor system 失效
标题翻译：多处理器系统中的片上数据传输
公开(公告)号：US06820143B2
公开(公告)日：2004-11-16
申请号：US10322127
申请日：2002-12-17
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichun Peter Liu , David Shippy , Thuong Quang Truong
IPC分类号： G06F1328
CPC分类号： G06F12/0817 , G06F12/0897
摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.
摘要翻译：提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。该系统包括第一和第二处理器。第一个处理器需要数据。该系统还包括与第一处理器通信的目录。目录接收到数据的数据请求，并包含有关数据存储位置的信息。缓存耦合到第二处理器。当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。

70. 发明授权

US06766442B1 Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value 失效
标题翻译：处理器和方法，其使用潜在的陈旧条件寄存器值来预测条件寄存器相关的条件分支指令
公开(公告)号：US06766442B1
公开(公告)日：2004-07-20
申请号：US09538992
申请日：2000-03-30
申请人： James Allan Kahle , Charles Roberts Moore
发明人： James Allan Kahle , Charles Roberts Moore
IPC分类号： G06F900
CPC分类号： G06F9/3804 , G06F9/30094 , G06F9/383 , G06F9/3846 , G06F9/3848
摘要： A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions, a condition register, and a branch prediction circuit that predicts a condition register-dependent branch instruction by reference to a potentially stale condition register value to produce a speculative instruction fetch address. In a preferred embodiment, the processor includes branch execution circuitry that subsequently determines if the speculative instruction fetch address is correct by reference to a non-stale value of the condition register.
摘要翻译：具有改进的分支预测精度的处理器包括执行顺序指令的至少一个执行单元，条件寄存器和分支预测电路，其通过参考潜在的陈旧条件寄存器值来预测与条件寄存器相关的分支指令，以产生推测指令取地址。在优选实施例中，处理器包括分支执行电路，其随后通过参考条件寄存器的非陈旧值确定推测指令提取地址是否正确。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式