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61. 发明授权

US08188574B2 Pedestal guard ring having continuous M1 metal barrier connected to crack stop 有权
标题翻译：具有连续的M1金属屏障的基座保护环连接到裂缝停止
公开(公告)号：US08188574B2
公开(公告)日：2012-05-29
申请号：US12704567
申请日：2010-02-12
申请人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
发明人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
IPC分类号： H01L29/72
CPC分类号： H01L23/585 , H01L21/76264 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.
摘要翻译：微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围芯片的有效部分。在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动离子在芯片的外围和有源部分之间移动。

62. 发明授权

US08173531B2 Structure and method to improve threshold voltage of MOSFETS including a high K dielectric 有权
标题翻译：提高包括高K电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US08173531B2
公开(公告)日：2012-05-08
申请号：US12535183
申请日：2009-08-04
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了形成阈值电压控制的半导体结构的方法，其中在至少暴露的具有大于氧化硅的介电常数的栅极介电材料的侧壁上形成共形氮化物衬里。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

63. 发明申请

US20120070947A1 INDUCING STRESS IN FIN-FET DEVICE 审中-公开
标题翻译：在Fin-FET器件中诱发应力
公开(公告)号：US20120070947A1
公开(公告)日：2012-03-22
申请号：US12883255
申请日：2010-09-16
申请人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Kingsuk Maitra
发明人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Kingsuk Maitra
IPC分类号： H01L21/336 , H01L21/263
CPC分类号： H01L29/66795 , H01L29/7843 , H01L29/7847 , H01L29/7849
摘要： A method of forming a fin-shaped field effect transistor (fin-FET) is disclosed. In one embodiment, the method comprises: partially amorphizing a fin overlying a substrate; forming a stress layer over a portion of the partially amorphized fin; annealing to impart stress in the partially amorphized fin to form a stressed fin; removing the stress layer from over the portion of stressed fin; and forming a gate over the stressed fin after the removing of the stress layer.
摘要翻译：公开了一种形成鳍状场效应晶体管（fin-FET）的方法。在一个实施方案中，所述方法包括：使覆盖在基底上的翅片部分非晶化; 在部分非晶化翅片的一部分上形成应力层; 退火以在部分非晶化翅片中施加应力以形成应力翅片; 从应力片的部分上去除应力层; 并且在去除应力层之后在应力翅片上形成栅极。

64. 发明申请

US20100200958A1 PEDESTAL GUARD RING HAVING CONTINUOUS M1 METAL BARRIER CONNECTED TO CRACK STOP 有权
标题翻译：带有连续断裂连续的M1金属障碍物的PEDESTAL GUARD RING
公开(公告)号：US20100200958A1
公开(公告)日：2010-08-12
申请号：US12704567
申请日：2010-02-12
申请人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
发明人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
IPC分类号： H01L23/00 , H01L21/762
CPC分类号： H01L23/585 , H01L21/76264 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.
摘要翻译：微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围芯片的有效部分。在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动离子在芯片的外围和有源部分之间移动。

65. 发明授权

US07358172B2 Poly filled substrate contact on SOI structure 有权
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07358172B2
公开(公告)日：2008-04-15
申请号：US11307762
申请日：2006-02-21
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

66. 发明申请

US20070196963A1 POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE 有权
标题翻译：多晶硅衬底接触SOI结构
公开(公告)号：US20070196963A1
公开(公告)日：2007-08-23
申请号：US11307762
申请日：2006-02-21
申请人： David Dobuzinsky , Byeong Kim , Effendi Leobandung , Munir Naeem , Brian Tessier
发明人： David Dobuzinsky , Byeong Kim , Effendi Leobandung , Munir Naeem , Brian Tessier
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

67. 发明授权

US06991998B2 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 失效
标题翻译：通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体
公开(公告)号：US06991998B2
公开(公告)日：2006-01-31
申请号：US10883883
申请日：2004-07-02
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
IPC分类号： H01L21/20
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

68. 发明申请

US20060001089A1 ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER 失效
标题翻译：超薄薄膜，高品质应变硅橡胶绝缘子，由弹性应变转移
公开(公告)号：US20060001089A1
公开(公告)日：2006-01-05
申请号：US10883883
申请日：2004-07-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/0392 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

69. 发明授权

US06858903B2 MOSFET device with in-situ doped, raised source and drain structures 有权
标题翻译： MOSFET器件具有原位掺杂，升高的源极和漏极结构
公开(公告)号：US06858903B2
公开(公告)日：2005-02-22
申请号：US10881449
申请日：2004-06-30
申请人： Wesley C. Natzle , Marc W. Cantell , Louis D. Lanzerotti , Effendi Leobandung , Brian L. Tessier , Ryan W. Wuthrich
发明人： Wesley C. Natzle , Marc W. Cantell , Louis D. Lanzerotti , Effendi Leobandung , Brian L. Tessier , Ryan W. Wuthrich
IPC分类号： H01L21/20 , H01L21/28 , H01L21/285 , H01L21/336 , H01L27/76
CPC分类号： H01L21/31116 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L21/28114 , H01L21/28247 , H01L21/28525 , H01L21/28562 , H01L29/66628
摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.
摘要翻译：一种用于制造FET器件的工艺。半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。可以加入氧化硅的毯层。可以在栅电极周围的氧化硅层上形成可选的氮化硅环。执行两个预清洗步骤。然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

70. 发明授权

US06825097B2 Triple oxide fill for trench isolation 有权
标题翻译：三重氧化物填充用于沟槽隔离
公开(公告)号：US06825097B2
公开(公告)日：2004-11-30
申请号：US10214510
申请日：2002-08-07
申请人： Klaus D. Beyer , Patricia A. O'Neil , Deborah A. Ryan , Peter Smeys , Effendi Leobandung
发明人： Klaus D. Beyer , Patricia A. O'Neil , Deborah A. Ryan , Peter Smeys , Effendi Leobandung
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76283
摘要： In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.
摘要翻译：在包括沟槽器件隔离的SOI的集成电路工艺中，通过三重填充工艺来解决沟槽填充中的空隙的问题，其中在底部拐角处具有凹陷的热氧化物侧壁被LPCVD沉积覆盖，所述LPCVD沉积填充凹陷，随后是无空隙的HDP沉积。致密化导致三种类型氧化物基本上相同的蚀刻速率。

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