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1. 发明授权

US08188574B2 Pedestal guard ring having continuous M1 metal barrier connected to crack stop 有权
标题翻译：具有连续的M1金属屏障的基座保护环连接到裂缝停止
公开(公告)号：US08188574B2
公开(公告)日：2012-05-29
申请号：US12704567
申请日：2010-02-12
申请人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
发明人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
IPC分类号： H01L29/72
CPC分类号： H01L23/585 , H01L21/76264 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.
摘要翻译：微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围芯片的有效部分。在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动离子在芯片的外围和有源部分之间移动。

2. 发明申请

US20100200958A1 PEDESTAL GUARD RING HAVING CONTINUOUS M1 METAL BARRIER CONNECTED TO CRACK STOP 有权
标题翻译：带有连续断裂连续的M1金属障碍物的PEDESTAL GUARD RING
公开(公告)号：US20100200958A1
公开(公告)日：2010-08-12
申请号：US12704567
申请日：2010-02-12
申请人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
发明人： Matthew S. Angyal , Mahender Kumar , Effendi Leobandung , Jay W. Strane
IPC分类号： H01L23/00 , H01L21/762
CPC分类号： H01L23/585 , H01L21/76264 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.
摘要翻译：微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围芯片的有效部分。在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动离子在芯片的外围和有源部分之间移动。

3. 发明授权

US07485510B2 Field effect device including inverted V shaped channel region and method for fabrication thereof 有权
标题翻译：包括倒V形沟道区域的场效应器件及其制造方法
公开(公告)号：US07485510B2
公开(公告)日：2009-02-03
申请号：US11538174
申请日：2006-10-03
申请人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
发明人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , H01L29/78648
摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.
摘要翻译：半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

4. 发明申请

US20080079037A1 FIELD EFFECT DEVICE INCLUDING INVERTED V SHAPED CHANNEL REGION AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：包括反相V形通道区域的场效应装置及其制造方法
公开(公告)号：US20080079037A1
公开(公告)日：2008-04-03
申请号：US11538174
申请日：2006-10-03
申请人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
发明人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/78648
摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.
摘要翻译：半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

5. 发明授权

US08723262B2 SOI FinFET with recessed merged fins and liner for enhanced stress coupling 有权
标题翻译： SOI FinFET具有凹入的合并翅片和衬垫，用于增强应力耦合
公开(公告)号：US08723262B2
公开(公告)日：2014-05-13
申请号：US13606893
申请日：2012-09-07
申请人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7843 , H01L29/6656 , H01L29/66795
摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.
摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷。然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。垂直硅化物提高了耐扩散性。

6. 发明授权

US08586449B1 Raised isolation structure self-aligned to fin structures 有权
标题翻译：升高的隔离结构自对准鳍结构
公开(公告)号：US08586449B1
公开(公告)日：2013-11-19
申请号：US13603872
申请日：2012-09-05
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
IPC分类号： H01L21/76
CPC分类号： H01L21/845 , H01L21/76229
摘要： Raised isolation structures can be formed at the same level as semiconductor fins over an insulator layer. A template material layer can be conformally deposited to fill the gaps among the semiconductor fins within each cluster of semiconductor fins on an insulator layer, while the space between adjacent clusters is not filled. After an anisotropic etch, discrete template material portions can be formed within each cluster region, while the buried insulator is physically exposed between cluster regions. A raised isolation dielectric layer is deposited and planarized to form raised isolation structures employing the template material portions as stopping structures. After removal of the template material portions, a cluster of semiconductor fins are located within a trench that is self-aligned to outer edges of the cluster of semiconductor fins. The trench can be employed to confine raised source/drain regions to be formed on the cluster of semiconductor fins.
摘要翻译：升高的隔离结构可以在与绝缘体层上的半导体鳍片相同的水平上形成。可以共形沉积模板材料层以填充绝缘体层上的每个半导体翅片簇内的半导体鳍片之间的间隙，而相邻簇之间的空间未被填充。在各向异性蚀刻之后，可以在每个簇区域内形成离散的模板材料部分，而埋入的绝缘体在簇区域之间物理暴露。沉积并平坦化凸起的隔离介电层以形成采用模板材料部分作为停止结构的凸起隔离结构。在去除模板材料部分之后，一组半导体鳍片位于与半导体鳍片簇的外边缘自对准的沟槽内。沟槽可以用来限制要形成在半导体鳍片簇上的凸起的源极/漏极区域。

7. 发明授权

US08513085B2 Structure and method to improve threshold voltage of MOSFETs including a high k dielectric 有权
标题翻译：提高包括高k电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US08513085B2
公开(公告)日：2013-08-20
申请号：US13409693
申请日：2012-03-01
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

8. 发明申请

US20130173214A1 METHOD AND STRUCTURE FOR INLINE ELECTRICAL FIN CRITICAL DIMENSION MEASUREMENT 审中-公开
标题翻译：在线电度关键尺寸测量的方法和结构
公开(公告)号：US20130173214A1
公开(公告)日：2013-07-04
申请号：US13343186
申请日：2012-01-04
申请人： Tenko Yamashita , Huiming Bu , Effendi Leobandung , Theodorus Eduardus Standaert
发明人： Tenko Yamashita , Huiming Bu , Effendi Leobandung , Theodorus Eduardus Standaert
IPC分类号： G01B7/02 , H01L23/58 , G06F19/00
CPC分类号： G01B7/023 , G01B2210/56 , H01L22/12 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method and test circuit for electrically measuring the critical dimension of a fin of a FinFET is disclosed. The method comprises measuring the resistance of a first gate test structure, measuring the resistance of a second gate test structure, computing a linear equation relating sheet resistance to gate width, computing a Y intercept value of the linear equation to derive an external resistance value, computing a sheet resistance value for the first gate test structure based on the external resistance value, measuring the resistance of a doped fin test structure, and computing a critical dimension of a fin based on the sheet resistance value.
摘要翻译：公开了一种用于电测量FinFET的鳍的临界尺寸的方法和测试电路。该方法包括测量第一栅极测试结构的电阻，测量第二栅极测试结构的电阻，计算相关薄层电阻与栅极宽度的线性方程，计算线性方程的Y截距值以导出外部电阻值，基于外部电阻值计算第一栅极测试结构的薄层电阻值，测量掺杂散热片测试结构的电阻，以及基于薄层电阻值计算散热片的临界尺寸。

9. 发明申请

US20110031554A1 STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC 有权
标题翻译：提高包括高K电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US20110031554A1
公开(公告)日：2011-02-10
申请号：US12535183
申请日：2009-08-04
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了形成阈值电压控制的半导体结构的方法，其中在至少暴露的具有大于氧化硅的介电常数的栅极介电材料的侧壁上形成共形氮化物衬里。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

10. 发明授权

US07268049B2 Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
标题翻译：具有超陡退化岛的MOSFET的制造和制造方法
公开(公告)号：US07268049B2
公开(公告)日：2007-09-11
申请号：US10954838
申请日：2004-09-30
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

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