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1. 发明授权

US06774000B2 Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures 有权
公开(公告)号：US06774000B2
公开(公告)日：2004-08-10
申请号：US10300239
申请日：2002-11-20
申请人： Wesley C. Natzle , Marc W. Cantell , Louis D. Lanzerotti , Effendi Leobandung , Brian L. Tessier , Ryan W. Wuthrich
发明人： Wesley C. Natzle , Marc W. Cantell , Louis D. Lanzerotti , Effendi Leobandung , Brian L. Tessier , Ryan W. Wuthrich
IPC分类号： H01L21336
CPC分类号： H01L21/31116 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L21/28114 , H01L21/28247 , H01L21/28525 , H01L21/28562 , H01L29/66628
摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

2. 发明授权

US06858903B2 MOSFET device with in-situ doped, raised source and drain structures 有权
标题翻译： MOSFET器件具有原位掺杂，升高的源极和漏极结构
公开(公告)号：US06858903B2
公开(公告)日：2005-02-22
申请号：US10881449
申请日：2004-06-30
申请人： Wesley C. Natzle , Marc W. Cantell , Louis D. Lanzerotti , Effendi Leobandung , Brian L. Tessier , Ryan W. Wuthrich
发明人： Wesley C. Natzle , Marc W. Cantell , Louis D. Lanzerotti , Effendi Leobandung , Brian L. Tessier , Ryan W. Wuthrich
IPC分类号： H01L21/20 , H01L21/28 , H01L21/285 , H01L21/336 , H01L27/76
CPC分类号： H01L21/31116 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L21/28114 , H01L21/28247 , H01L21/28525 , H01L21/28562 , H01L29/66628
摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.
摘要翻译：一种用于制造FET器件的工艺。半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。可以加入氧化硅的毯层。可以在栅电极周围的氧化硅层上形成可选的氮化硅环。执行两个预清洗步骤。然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

3. 发明授权

US06900519B2 Diffused extrinsic base and method for fabrication 有权
公开(公告)号：US06900519B2
公开(公告)日：2005-05-31
申请号：US10865138
申请日：2004-06-10
申请人： Marc W. Cantell , James S. Dunn , David L. Harame , Robb A. Johnson , Louis D. Lanzerotti , Stephen A. St. Onge , Brian L. Tessier , Ryan W. Wuthrich
发明人： Marc W. Cantell , James S. Dunn , David L. Harame , Robb A. Johnson , Louis D. Lanzerotti , Stephen A. St. Onge , Brian L. Tessier , Ryan W. Wuthrich
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/10 , H01L27/082
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/1004
摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

4. 发明授权

US06869854B2 Diffused extrinsic base and method for fabrication 失效
标题翻译：扩散的外在基础和制造方法
公开(公告)号：US06869854B2
公开(公告)日：2005-03-22
申请号：US10064476
申请日：2002-07-18
申请人： Marc W. Cantell , James S. Dunn , David L. Harame , Robb A. Johnson , Louis D. Lanzerotti , Stephen A. St. Onge , Brian L. Tessier , Ryan W. Wuthrich
发明人： Marc W. Cantell , James S. Dunn , David L. Harame , Robb A. Johnson , Louis D. Lanzerotti , Stephen A. St. Onge , Brian L. Tessier , Ryan W. Wuthrich
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/10 , H01L23/62
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/1004
摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.
摘要翻译：本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。掺杂剂的这种扩散形成至少一部分外在碱。特别地，通过扩散形成与本征基区相邻的部分。该解决方案避免了植入外在基础的传统解决方案所引起的问题。具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。这种降低的损伤增强了掺杂剂扩散到本征基质中。另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

5. 发明授权

US07592245B2 Poly filled substrate contact on SOI structure 失效
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07592245B2
公开(公告)日：2009-09-22
申请号：US12014127
申请日：2008-01-15
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

6. 发明授权

US07358172B2 Poly filled substrate contact on SOI structure 有权
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07358172B2
公开(公告)日：2008-04-15
申请号：US11307762
申请日：2006-02-21
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

7. 发明申请

US20090159934A1 FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE 有权
标题翻译：具有减小厚度门的场效应装置
公开(公告)号：US20090159934A1
公开(公告)日：2009-06-25
申请号：US12274758
申请日：2008-11-20
申请人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
发明人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译：通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。在形成与栅电极相邻的间隔层之后，栅电极变薄。此外，间隔层的高度也可以减小。间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。升高的源极/漏极层可以位于本征源极/漏极区域上。凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

8. 发明授权

US08492803B2 Field effect device with reduced thickness gate 有权
标题翻译：具有减小厚度门的场效应装置
公开(公告)号：US08492803B2
公开(公告)日：2013-07-23
申请号：US12274758
申请日：2008-11-20
申请人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
发明人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译：通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。在形成与栅电极相邻的间隔层之后，栅电极变薄。此外，间隔层的高度也可以减小。间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。升高的源极/漏极层可以位于本征源极/漏极区域上。凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

9. 发明授权

US07459382B2 Field effect device with reduced thickness gate 有权
标题翻译：具有减小厚度门的场效应装置
公开(公告)号：US07459382B2
公开(公告)日：2008-12-02
申请号：US11308432
申请日：2006-03-24
申请人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
发明人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
IPC分类号： H01L21/44 , H01L21/28
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译：通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。在形成与栅电极相邻的间隔层之后，栅电极变薄。此外，间隔层的高度也可以减小。间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。升高的源极/漏极层可以位于本征源极/漏极区域上。凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

10. 发明申请

US20070221964A1 FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE 有权
标题翻译：具有减小厚度门的场效应装置
公开(公告)号：US20070221964A1
公开(公告)日：2007-09-27
申请号：US11308432
申请日：2006-03-24
申请人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
发明人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
IPC分类号： H01L29/76
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译：通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。在形成与栅电极相邻的间隔层之后，栅电极变薄。此外，间隔层的高度也可以减小。间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。升高的源极/漏极层可以位于本征源极/漏极区域上。凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

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