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61. 发明授权

US08395922B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08395922B2
公开(公告)日：2013-03-12
申请号：US13035134
申请日：2011-02-25
申请人： Mitsuhiro Noguchi , Kenji Sawamura , Takeshi Kamigaichi , Katsuaki Isobe
发明人： Mitsuhiro Noguchi , Kenji Sawamura , Takeshi Kamigaichi , Katsuaki Isobe
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C16/0483 , G11C16/26
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。第一读出放大器电路连接到多个第一互连。第二读出放大器电路连接到多个第二互连。互连上表面的高度相等。沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

62. 发明授权

US08315094B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08315094B2
公开(公告)日：2012-11-20
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

63. 发明授权

US07978517B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07978517B2
公开(公告)日：2011-07-12
申请号：US12719686
申请日：2010-03-08
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other, wherein a bit line that is selected by a sense amplifier is charged in a state where a drain-side select gate line, a source-side select gate line and a p-type semiconductor substrate are set at a ground potential, and source lines, n-type wells, p-type wells, and a bit line that is not selected by the sense amplifier are in a floating state.
摘要翻译：在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成所述存储单元单元具有彼此连接的多个电可重写存储单元，其中由读出放大器选择的位线在漏极侧选择栅极线，源极侧选择栅极线路和p型半导体衬底设置为接地电位，源极线，n型阱，p型阱和未被读出放大器选择的位线处于浮置状态。

64. 发明申请

US20060034120A1 Non-volatile semiconductor memory device 有权
公开(公告)号：US20060034120A1
公开(公告)日：2006-02-16
申请号：US11193442
申请日：2005-08-01
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.

65. 发明申请

US20050207237A1 Semiconductor memory device provided with constant-current circuit having current trimming function 失效
标题翻译：具有具有电流修整功能的恒流电路的半导体存储器件
公开(公告)号：US20050207237A1
公开(公告)日：2005-09-22
申请号：US11045383
申请日：2005-01-31
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/06 , G11C29/02 , H03B1/00
CPC分类号： G11C29/028 , G11C29/02 , G11C2029/5006
摘要： A semiconductor memory device includes a memory cell unit including at least one semiconductor memory cell, a voltage generating circuit which produces an operating voltage to which reference is made in performing a predetermined operation on the memory cell unit. The device further includes a constant-current circuit capable of a current trimming operation and adapted to supply a constant current to the voltage generating circuit.
摘要翻译：半导体存储器件包括存储单元单元，该存储单元单元包括至少一个半导体存储单元，产生电路的电压产生电路，该电压产生电路在对存储单元单元执行预定操作时进行参考。该装置还包括能够进行电流调整操作并适于向电压产生电路提供恒定电流的恒流电路。

66. 发明授权

US06731149B2 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
标题翻译：用于产生与时钟信号同步的信号的同步电路
公开(公告)号：US06731149B2
公开(公告)日：2004-05-04
申请号：US10003312
申请日：2001-12-06
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03K501
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.
摘要翻译：用于正向脉冲的第一延迟线和用于反向脉冲的第二延迟线由单位延迟元件组成。状态保持部根据沿着第一延迟线传送的正向脉冲的传送位置来确定第二延迟线上的反向脉冲的输入位置。在构成第一和第二延迟线的单位延迟元件中，可以通过增加与脉冲信号的上升相关的晶体管的电流驱动能力来提高同步精度。

67. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

68. 发明申请

US20120002478A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120002478A1
公开(公告)日：2012-01-05
申请号：US13236300
申请日：2011-09-19
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
摘要翻译：当电压电平检测器检测到电源电压达到需要恢复操作的恢复电压电平时，信号发生器产生用于指示恢复操作的恢复操作指令信号。如果某些操作模式在其他情况下被执行和验证，则恢复操作指令信号无效。

69. 发明申请

US20100329026A1 SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER 审中-公开
标题翻译：具有充电累积层的半导体存储器件
公开(公告)号：US20100329026A1
公开(公告)日：2010-12-30
申请号：US12822703
申请日：2010-06-24
申请人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
发明人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元，第一和第二选择晶体管，源极线，温度监视器和源极线电压控制器。存储单元串联连接在第一选择晶体管的源极和第二选择晶体管的漏极之间。温度监视器监视半导体衬底的温度。源极线电压控制器在读取操作中以源极线和半导体衬底之间的电位差随着由温度监视器监测的温度的升高而增加的电压施加电压，在第二选择晶体管的源极和半导体衬底之间施加反向偏压。

70. 发明申请

US20080117687A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20080117687A1
公开(公告)日：2008-05-22
申请号：US11940736
申请日：2007-11-15
申请人： Mitsuaki Honma , Katsuaki Isobe
发明人： Mitsuaki Honma , Katsuaki Isobe
IPC分类号： G11C16/08 , G11C8/00
CPC分类号： G11C16/0483 , G11C16/20 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/48 , G11C2029/5004
摘要： A nonvolatile semiconductor memory for setting control voltages to be supplied to an internal circuit, to an external reference voltage inputted from outside, has a parameter control circuit. The parameter control circuit causes a parameter register to sequentially output the plurality of parameters to a voltage generating control circuit. The parameter control circuit counts, for a fixed period of time, the number of oscillations of each of the trimming flag signals sequentially outputted from the voltage generating control circuit in response to the parameters. The parameter control circuit stores counted values corresponding to the parameters. The parameter control circuit selects the parameter having a maximum counted value as a parameter corresponding to the control voltage closest to the external reference voltage.
摘要翻译：用于将向内部电路提供的控制电压设置为从外部输入的外部参考电压的非易失性半导体存储器具有参数控制电路。参数控制电路使参数寄存器顺序地将多个参数输出到电压产生控制电路。参数控制电路在固定的时间段内，根据参数从电压产生控制电路顺序输出的每个修整标志信号的振荡次数进行计数。参数控制电路存储对应于参数的计数值。参数控制电路选择具有最大计数值的参数作为与最接近外部参考电压的控制电压对应的参数。

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