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61. 发明授权

US5732022A Non-volatile semiconductor memory device 失效
公开(公告)号：US5732022A
公开(公告)日：1998-03-24
申请号：US812765
申请日：1997-03-06
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C16/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

62. 发明授权

US5576994A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5576994A
公开(公告)日：1996-11-19
申请号：US428060
申请日：1995-04-25
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C7/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

63. 发明授权

US5546351A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5546351A
公开(公告)日：1996-08-13
申请号：US326281
申请日：1994-10-20
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

64. 发明授权

US5384742A Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5384742A
公开(公告)日：1995-01-24
申请号：US30343
申请日：1993-03-25
申请人： Tadashi Miyakawa , Masamichi Asano
发明人： Tadashi Miyakawa , Masamichi Asano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/16 , G11C16/10 , G11C16/12 , G11C16/3418
摘要： A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.
摘要翻译： PCT No.PCT / JP91 / 01272 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT 1991年9月25日PCT公布。出版物WO92 / 05560 日期：1992年4月2日。存储单元阵列被分成多个块。在更改块（选择块）的数据时，将调节电压施加到另一个块（未选择块）中的存储单元的源极或控制栅极，以缓和浮动栅极和源极/漏极之间的应力，从而防止写入错误和擦除错误。在编程操作中，未选择的块中的存储单元的源极和漏极被均衡以控制控制栅极和源极/漏极之间的电场，并且不流过沟道电流，从而防止写入错误。在执行负电压擦除方法时，在将未选块中的单元的源极线和字线设置为擦除电压之前，源极和字线被均衡。在擦除操作之后释放均衡操作，从而防止未选择的单元的故障。

65. 发明授权

US5361227A Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US5361227A
公开(公告)日：1994-11-01
申请号：US992653
申请日：1992-12-18
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

66. 发明授权

US5210048A Nonvolatile semiconductor memory device with offset transistor and method for manufacturing the same 失效
标题翻译：具有偏置晶体管的非易失性半导体存储器件及其制造方法
公开(公告)号：US5210048A
公开(公告)日：1993-05-11
申请号：US924521
申请日：1992-08-04
申请人： Atsushi Shoji , Masamichi Asano , Tadashi Miyakawa , Tadayuki Taura , Michiharu Inami
发明人： Atsushi Shoji , Masamichi Asano , Tadashi Miyakawa , Tadayuki Taura , Michiharu Inami
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0425
摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.
摘要翻译：在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。在基板的源极和漏极区域上形成第一绝缘膜。在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。在第二绝缘膜上形成浮栅。在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。第一绝缘膜和杂质区用作存储单元的元件隔离区。

67. 发明申请

US20100030943A1 Semiconductor Memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20100030943A1
公开(公告)日：2010-02-04
申请号：US10589375
申请日：2005-02-09
申请人： Kengo Maeda , Akira Tanigawa , Masuji Nishiyama , Shoichi Ohori , Makoto Hirano , Hiroshi Takashima , Shinji Matoba , Masamichi Asano
发明人： Kengo Maeda , Akira Tanigawa , Masuji Nishiyama , Shoichi Ohori , Makoto Hirano , Hiroshi Takashima , Shinji Matoba , Masamichi Asano
IPC分类号： G06F12/00
CPC分类号： G11C16/32 , G11C7/1027 , G11C7/1072
摘要： A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal.
摘要翻译：具有与时钟信号同步的突发模式读取功能的半导体存储器包括由多个存储器单元组成的存储器阵列，用于将接收到的地址的上部组释放为存储器访问地址的同步读取控制电路和下部组的接收地址作为与时钟信号同步的突发地址;读出放大器，用于释放由存储器地址选择的每个存储器单元的输出数据，解码器，用于解码突发地址;地址锁存器，用于锁存解码的突发地址与时钟信号同步，用于保存输出数据并选择由地址锁存器的突发地址确定的输出数据中的相应一个的页选择器，以及用于与时钟信号同步地锁存输出数据的输出锁存器。

68. 发明申请

US20070279111A1 Dll Circuit 审中-公开
标题翻译： Dll电路
公开(公告)号：US20070279111A1
公开(公告)日：2007-12-06
申请号：US10589403
申请日：2005-02-09
申请人： Kengo Maeda , Akira Tanigawa , Masuji Nishiyama , Shoichi Ohori , Makoto Hirano , Hiroshi Takashima , Shinji Matoba , Masamichi Asano
发明人： Kengo Maeda , Akira Tanigawa , Masuji Nishiyama , Shoichi Ohori , Makoto Hirano , Hiroshi Takashima , Shinji Matoba , Masamichi Asano
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222 , G11C16/32 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03K5/133 , H03K2005/00019 , H03L7/0818
摘要： A DLL circuit having a phase comparison circuit for comparing phases of a reference clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched at a logic “1” by start of 1 clock cycle of an internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting duration time of the logic “1” of the first signal input by the variable delay addition circuit through the dummy delay until the end of the 1 clock cycle of the internal clock and setting an initial value of delay amount of the variable delay addition circuit based on the duration time.
摘要翻译：具有用于比较参考时钟和延迟时钟的相位的相位比较电路的DLL电路和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括用于输入锁存在逻辑上的第一信号的装置通过在突发开始时的虚拟延迟，将内部时钟的1个时钟周期开始到可变延迟加法电路的“1”和用于检测由可变延迟输入的第一信号的逻辑“1”的持续时间的装置通过虚拟延迟的加法电路，直到内部时钟的1个时钟周期结束，并且基于持续时间设置可变延迟加法电路的延迟量的初始值。

69. 发明授权

US5818791A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5818791A
公开(公告)日：1998-10-06
申请号：US826152
申请日：1997-03-27
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

70. 发明授权

US5724300A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5724300A
公开(公告)日：1998-03-03
申请号：US784927
申请日：1997-01-16
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

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