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61. 发明授权

US06603211B2 Method and system for providing a robust alignment mark at thin oxide layers 失效
公开(公告)号：US06603211B2
公开(公告)日：2003-08-05
申请号：US09784907
申请日：2001-02-15
申请人： Michael K. Templeton , Hao Fang , Maria C. Chan , King Wai Kelwin Ko
发明人： Michael K. Templeton , Hao Fang , Maria C. Chan , King Wai Kelwin Ko
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

62. 发明授权

US06495435B2 Method for improved control of lines adjacent to a select gate using a mask assist feature 失效
标题翻译：一种使用掩模辅助功能改进与选择门相邻的线的控制的方法
公开(公告)号：US06495435B2
公开(公告)日：2002-12-17
申请号：US09788246
申请日：2001-02-15
申请人： Michael K. Templeton , Hao Fang , Maria C. Chan
发明人： Michael K. Templeton , Hao Fang , Maria C. Chan
IPC分类号： H01L2120
CPC分类号： H01L27/11521 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.
摘要翻译：公开了一种用于在半导体存储器件中提供多条线的方法和系统。该方法和系统包括提供半导体衬底，提供多条线并提供相邻特征。多条线包括与相邻特征相邻的相邻线。多条线中的每条线具有对于多根线中的每条线基本相同的线宽度。优选地，利用掩模形成多条线以打印多条线和相邻特征的物理掩模。掩模包括用于相邻行的至少第一多边形和用于相邻特征的至少第二多边形之间的掩模辅助特征。掩模辅助特征具有足够大的尺寸以影响相邻线的宽度，并且足够小以防止相应的特征被印刷在物理掩模上。该方法和系统还优选地包括去除由物理掩模的图案暴露的材料层的第二部分以形成多条线。

63. 发明授权

US06445051B1 Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权
标题翻译：用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限
公开(公告)号：US06445051B1
公开(公告)日：2002-09-03
申请号：US09563797
申请日：2000-05-02
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28273
摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供多个触点的方法和系统。闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。该方法和系统还包括蚀刻绝缘层以提供多个接触孔。绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤不会蚀刻穿过多个场绝缘区域。该方法和系统还包括用导体填充多个接触孔。

64. 发明授权

US06436778B1 Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process 有权
标题翻译：再氧化方法提高隧道氮化物氧化工艺中的外围栅极氧化物完整性
公开(公告)号：US06436778B1
公开(公告)日：2002-08-20
申请号：US09879738
申请日：2001-06-12
申请人： Hao Fang , Yue-song He
发明人： Hao Fang , Yue-song He
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11536
摘要： A process for fabricating a semiconductor device 20 that includes providing semiconductor substrate 28 having a core region 24 and a peripheral gate region 26. The semiconductor substrate 28 has at least one shallow trench isolation region 30 and at least one nitrogen-contaminated region 36 in the peripheral gate region 26. A tunnel oxide layer 34 overlies the semiconductor substrate 28 and a first polysilicon layer 38 overlies the tunnel oxide layer 34 in the core region 24. An ONO layer 40 overlies the first polysilicon layer 38 in the core region 24. The process further includes growing a sacrificial oxide layer 42 overlying the nitrogen-contaminated region 36 in the peripheral gate region 26, wherein oxygen from within the sacrificial oxide layer 42 diffuses into the nitrogen-contaminated region 36 and forms silicon dioxide. By allowing oxygen from within the sacrificial oxide layer 42 to diffuse into the nitrogen-contaminated region 36 and form silicon dioxide, the nitrogen 56 can be removed from within the semiconductor substrate 28 by removing the silicon dioxide.
摘要翻译：一种制造半导体器件20的方法，其包括提供具有芯区24和外围栅区26的半导体衬底28.半导体衬底28具有至少一个浅沟槽隔离区30和至少一个氮污染区36 隧道氧化物层34覆盖在半导体衬底28上，并且第一多晶硅层38覆盖在芯区域24中的隧道氧化物层34上.OOO层40覆盖在核心区域24中的第一多晶硅层38上。工艺还包括在外围栅极区域26中生长覆盖氮污染区域36的牺牲氧化物层42，其中来自牺牲氧化物层42内的氧气扩散到氮污染区域36中并形成二氧化硅。通过允许牺牲氧化物层42内的氧气扩散到氮污染区域36中并形成二氧化硅，可以通过去除二氧化硅从半导体衬底28内去除氮56。

65. 发明授权

US06429479B1 Nand flash memory with specified gate oxide thickness 有权
标题翻译： Nand闪存，具有指定的栅极氧化物厚度
公开(公告)号：US06429479B1
公开(公告)日：2002-08-06
申请号：US09522247
申请日：2000-03-09
申请人： K. Michael Han , Hao Fang , Masaaki Higashitani
发明人： K. Michael Han , Hao Fang , Masaaki Higashitani
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85 Å-105 Å. For single tunnel gate approach, a careful selection of the medium doped source/drain region implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentrations of 1013-1014/cm2.
摘要翻译：公开了用于制造NAND存储器串的单通道栅极氧化工艺，其中选择晶体管的栅极氧化物和浮动栅极存储晶体管是在一个氧化步骤中制造的。选择栅极晶体管和浮动栅极存储晶体管的氧化物厚度为85埃-105。对于单通道栅极方法，对NAND存储器串的正常功能需要仔细选择中等掺杂源极/漏极区域注入条件。在一个实施例中，中等掺杂源极/漏极区掺杂有浓度为1013-1014 / cm2的砷。

66. 发明授权

US06420240B1 Method for reducing the step height of shallow trench isolation structures 有权
标题翻译：降低浅沟槽隔离结构台阶高度的方法
公开(公告)号：US06420240B1
公开(公告)日：2002-07-16
申请号：US09611701
申请日：2000-07-08
申请人： Wenge Yang , John Jianshi Wang , Hao Fang
发明人： Wenge Yang , John Jianshi Wang , Hao Fang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.
摘要翻译：在一个实施例中，用于降低浅沟槽隔离结构的台阶高度的方法包括以下动作：（a）在半导体衬底上形成硬掩模以限定沟槽，（b）形成沟槽，（c）用电介质材料，（d）使介电材料平坦化，（e）用抗蚀剂掩模代替硬掩模，（f）蚀刻电介质材料以降低其台阶高度，和（g）去除抗蚀剂掩模。在另一个实施例中，用于限定沟槽的硬掩模在电介质材料的回蚀刻期间使用。在另一个实施例中，用于限定沟槽的硬掩模在电介质材料平坦化之前被部分剥离以降低其台阶高度。

67. 发明授权

US06369433B1 High voltage transistor with low body effect and low leakage 有权
标题翻译：具有低体积效应和低泄漏的高压晶体管
公开(公告)号：US06369433B1
公开(公告)日：2002-04-09
申请号：US09182525
申请日：1998-10-30
申请人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
发明人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
IPC分类号： H01L2994
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/823814 , H01L29/1041 , H01L29/66825
摘要： A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.
摘要翻译：形成具有低泄漏和低体效应的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括在通道区域上提供场注入阻挡掩模，从而产生具有低体效应的晶体管，场注入阻挡掩模具有适当的开口，使得场注入发生在通道的边缘，从而减少泄漏。

68. 发明授权

US06350627B1 Interlevel dielectric thickness monitor for complex semiconductor chips 有权
标题翻译：复合半导体芯片的层间电介质厚度监测器
公开(公告)号：US06350627B1
公开(公告)日：2002-02-26
申请号：US09548741
申请日：2000-04-13
申请人： Tho Le La , John Jianshi Wang , Hao Fang
发明人： Tho Le La , John Jianshi Wang , Hao Fang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/76801 , H01L22/12
摘要： A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box. Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
摘要翻译：一种在半导体芯片内测量不同类型的多个结构之上的电介质层的厚度的方法。该方法包括以下步骤：在半导体芯片上形成多个监视盒，使得所述多个监视盒中的每一个表示半导体芯片内的结构类型，并具有与多种不同结构类型之一基本相同的台阶高度 ; 在所述半导体芯片上形成介电层; 以及测量所述多个监视盒中的至少一个的所述电介质层的厚度，其中所述厚度表示所述电介质层的厚度，所述电介质层的厚度在由所述监视盒所表示的结构类型的结构之上。还公开了允许用于精确的电介质厚度测量。芯片包括：位于半导体芯片内的表面上的不同类型的多个结构; 以及位于半导体芯片内的所述表面上的多个监视器盒，可以在其上进行介电厚度的测量，其中多个监视盒中的每一个表示半导体芯片内的结构类型。

69. 发明授权

US06306706B1 Method and system for fabricating a flash memory array 有权
标题翻译：用于制造闪存阵列的方法和系统
公开(公告)号：US06306706B1
公开(公告)日：2001-10-23
申请号：US09538922
申请日：2000-03-30
申请人： Maria C. Chan , Hao Fang , Mark S. Chang
发明人： Maria C. Chan , Hao Fang , Mark S. Chang
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531 , Y10T29/41
摘要： A method and system for fabricating a flash memory array comprising a core area and a periphery area is disclosed. The method and system comprises depositing a layer of poly2 over the core area and the periphery area, selectively etching the core area, and selectively etching the poly2 only in the periphery area wherein the occurrence of stringers is reduced. Through the use of the preferred embodiment of the present invention, the core and periphery areas are etched separately after the deposition of the poly2, thereby reducing the occurrence of stringers at the core/periphery interface. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent transistors is substantially reduced.
摘要翻译：公开了一种用于制造包括芯区域和外围区域的闪存阵列的方法和系统。该方法和系统包括在核心区域和外围区域上沉积多晶硅层2，选择性地蚀刻核心区域，并且仅在缩小桁条发生的周边区域中选择性地蚀刻聚二元体。通过使用本发明的优选实施例，在沉积poly2之后分别蚀刻芯和外围区域，从而减少在芯/周边界面处的桁条的发生。因此，相邻晶体管之间不需要的电短路径的发生显着减少。

70. 发明授权

US06218689B1 Method for providing a dopant level for polysilicon for flash memory devices 有权
标题翻译：为闪存器件提供多晶硅掺杂剂水平的方法
公开(公告)号：US06218689B1
公开(公告)日：2001-04-17
申请号：US09369638
申请日：1999-08-06
申请人： Kent Kuohua Chang , Kenneth Wo-Wai Au , Hao Fang
发明人： Kent Kuohua Chang , Kenneth Wo-Wai Au , Hao Fang
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/11524
摘要： The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5×1018 and 8×1019 ions/cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.
摘要翻译：本发明提供了一种方法和NAND型闪速存储器件。该方法包括在衬底的选择晶体管区域和衬底的存储单元区域中形成选择栅极氧化物层和隧道氧化物层; 在选择栅极氧化物层和隧道氧化物层上形成掺杂非晶硅层，掺杂非晶硅层具有同时避免选择晶体管字线高电阻问题和电荷增益/电荷损失问题的掺杂剂水平; 在所述掺杂非晶硅层上形成绝缘层; 在所述绝缘层上形成控制栅极层; 以及至少蚀刻所述掺杂的非晶硅层，所述绝缘层和所述控制栅极层，以形成至少一个存储单元堆叠结构和至少一个选择晶体管堆叠结构。在优选实施例中，形成闪存单元的浮动栅极和器件的选择晶体管的选择栅极的多晶硅层掺杂有大约5×1018和8×1019离子/ cm3的磷。利用该掺杂剂水平，选择晶体管的控制栅极的接触电阻低，从而保持器件的字线电阻率低。同时，掺杂剂对闪存单元的隧道氧化物的污染是有限的，允许浮置栅极和隧道氧化物之间的界面平滑，这防止了电荷增益/损耗问题。因此，装置的可靠性增加。

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