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61. 发明授权

US07616515B2 Integrated electronic device having a low voltage electric supply 有权
标题翻译：具有低电压电源的集成电子设备
公开(公告)号：US07616515B2
公开(公告)日：2009-11-10
申请号：US11401523
申请日：2006-04-11
申请人： Giovanni Campardo , Gian Pietro Vanalli , Pier Paolo Stoppino , Roberto Dossi , Aldo Losavio
发明人： Giovanni Campardo , Gian Pietro Vanalli , Pier Paolo Stoppino , Roberto Dossi , Aldo Losavio
IPC分类号： G11C5/14
CPC分类号： G11C16/30
摘要： An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the at least one booster and associated therewith in a “system in a package configuration.”
摘要翻译：集成电子设备包括至少一个电源引脚和耦合到所述至少一个电源引脚的至少一个升压器。而且，至少有一个集成电路由至少一个升压器供电并与“封装配置中的系统”相关联。

62. 发明授权

US06944061B2 Single cell erasing method for recovering memory cells under programming disturbs in non volatile semiconductor memory devices 失效
标题翻译：用于在非易失性半导体存储器件中的编程干扰下恢复存储单元的单单元擦除方法
公开(公告)号：US06944061B2
公开(公告)日：2005-09-13
申请号：US10724022
申请日：2003-11-26
申请人： Emilio Camerlenghi , Giovanni Campardo , Tecla Ghilardi
发明人： Emilio Camerlenghi , Giovanni Campardo , Tecla Ghilardi
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3431 , G11C16/3404 , G11C16/3418
摘要： The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organized in rows, or word lines, and columns, or bit lines.This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage.With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.
摘要翻译：本发明涉及一种用于在非易失性半导体存储器电子器件中读取或编程干扰的存储器单元中恢复存储单元的特定单元擦除方法，该非易失性半导体存储器电子器件包括扇区中的单元矩阵分割并以行或字线，列或位线组织。这种存储器件通常提供具有随后的测试阶段（擦除验证）的扇区擦除算法的应用; 但是根据本发明的方法通过在每个单个字线上施加在擦除整个扇区期间使用的负电压并且在每个单电池的漏极端子上施加编程电压来逐位擦除。利用这种选择性偏置，可以执行单个单元，或逐位擦除，允许在读取或编程干扰的情况下的所有单元增加其要恢复的原始阈值。

63. 发明授权

US06587914B2 Non-volatile memory capable of autonomously executing a program 有权
标题翻译：能够自主执行程序的非易失性存储器
公开(公告)号：US06587914B2
公开(公告)日：2003-07-01
申请号：US09349702
申请日：1999-07-08
申请人： Giovanni Campardo
发明人： Giovanni Campardo
IPC分类号： G06F1200
CPC分类号： G11C7/00 , G06F9/262 , G11C7/1006
摘要： A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to the memory device, that in a first operating mode are controlled by devices outside to the memory device, and transmit signals to the matrix of memory cells, which are adapted to decode the received signals and to transmit in turn output decoded signals through the output buffer block. A command block is provided that is activatable through an external control signal and once activated, it puts the memory device in a second operating mode in which the command block receives at least a part of the signals in output of said matrix of memory cells and, after having processed them, transmits internal address signals to the address buffer block. This provides a feedback inside the memory device capable of making the same able to autonomously execute a succession of instructions stored in the matrix of memory cells.
摘要翻译：一种非易失性半导体存储器件，包括地址缓冲器块，存储器单元矩阵和输出缓冲器块。地址缓冲器块接收存储器件外部的输入信号，在第一操作模式中由存储器件外部的器件控制，并将信号发送到存储器单元矩阵，该存储器单元矩阵适于对接收的信号进行解码并传输反过来通过输出缓冲块输出解码信号。提供了可通过外部控制信号激活的命令块，一旦被激活，它将存储器件置于第二操作模式，其中命令块在存储器单元矩阵的输出中接收至少一部分信号，在处理它们之后，将内部地址信号发送到地址缓冲块。这提供了能够使得能够自主地执行存储在存储器单元矩阵中的一系列指令的存储器件内的反馈。

64. 发明授权

US06396168B2 Programmable logic arrays 有权
标题翻译：可编程逻辑阵列
公开(公告)号：US06396168B2
公开(公告)日：2002-05-28
申请号：US09782173
申请日：2001-02-12
申请人： Stefano Ghezzi , Donato Ferrario , Emilio Yero , Giovanni Campardo
发明人： Stefano Ghezzi , Donato Ferrario , Emilio Yero , Giovanni Campardo
IPC分类号： H03K19096
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1778 , Y10T307/505
摘要： A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.
摘要翻译：可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。属于同一列的晶体管可以彼此串联连接。串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。

65. 发明授权

US06215329B1 Output stage for a memory device and for low voltage applications 失效
标题翻译：用于存储器件和低电压应用的输出级
公开(公告)号：US06215329B1
公开(公告)日：2001-04-10
申请号：US08899228
申请日：1997-07-23
申请人： Giovanni Campardo , Stefano Zanardi , Andrea Ghilardelli
发明人： Giovanni Campardo , Stefano Zanardi , Andrea Ghilardelli
IPC分类号： H03K19094
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1069
摘要： The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage and a voltage regulator for the control terminals of said transistors. The regulator is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage by boosting the voltage applied to said control terminals.
摘要翻译：本发明涉及一种用于电子存储器件的输出级和用于低电源电压的应用，并且是包括上拉/下拉型的最后一级的类型，其由插入在初级参考电源电压和二次参考电压和用于所述晶体管的控制端的电压调节器。调节器是使用至少一个自举电容器的升压器，其通过升高施加到所述控制端子的电压来增加在最后级中流动的电流。

66. 发明授权

US5748528A EEPROM memory device with simultaneous read and write sector capabilities 失效
标题翻译：具有同时读写扇区能力的EEPROM存储器件
公开(公告)号：US5748528A
公开(公告)日：1998-05-05
申请号：US642813
申请日：1996-05-03
申请人： Giovanni Campardo , Lorenzo Bedarida , Giuseppe Fusillo , Andrea Silvagni
发明人： Giovanni Campardo , Lorenzo Bedarida , Giuseppe Fusillo , Andrea Silvagni
IPC分类号： G11C17/00 , G11C7/18 , G11C8/10 , G11C8/12 , G11C16/02 , G11C16/06 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C7/18 , G11C8/10 , G11C8/12 , G11C2216/22
摘要： A memory device having a memory array, a row decoding unit, a column decoding unit, and a control unit; the memory array presents global bit lines extending along the whole of the array and connected to respective local bit lines, one for each of the sectors; a switch is provided between the global bit lines and each respective local bit line to selectively connect a selected global bit line and only one of the associated local bit lines; and the switches are controlled by local decoding units over control lines, to address the sectors independently and so perform operations (read, erase, write) simultaneously in two different sectors in different rows and columns.
摘要翻译：具有存储器阵列，行解码单元，列解码单元和控制单元的存储器件; 存储器阵列呈现沿整个阵列延伸并连接到相应的局部位线的全局位线，每个扇区一个; 在全局位线和每个相应的局部位线之间提供开关以选择性地连接所选择的全局位线和仅一个相关联的局部位线; 并且开关由控制线上的本地解码单元控制，以独立地寻址扇区，并且因此在不同行和列中的两个不同扇区中同时执行操作（读取，擦除，写入）。

67. 发明授权

US5729492A Sense amplifier having capacitively coupled input for offset compensation 失效
标题翻译：具有用于偏移补偿的电容耦合输入的感测放大器
公开(公告)号：US5729492A
公开(公告)日：1998-03-17
申请号：US639192
申请日：1996-04-26
申请人： Giovanni Campardo
发明人： Giovanni Campardo
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A sense amplifier circuit for a semiconductor memory device comprises a first current/voltage converter for convening a current of a memory cell to be read into a voltage signal, a second current/voltage converter for converting a reference current into a reference voltage signal, and a voltage comparator for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises a capacitive decoupler for decoupling the voltage signal from the comparator, and circuitry for providing the capacitive decoupler with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.
摘要翻译：一种用于半导体存储器件的读出放大器电路包括用于将待读取的存储单元的电流转换为电压信号的第一电流/电压转换器，将参考电流转换为参考电压信号的第二电流/电压转换器，以及电压比较器，用于将电压信号与参考电压信号进行比较。感测放大器电路包括用于去耦电压信号与比较器的电容去耦器，以及电路，用于向电容解耦器提供适合于通过叠加在存储器电流上的偏置电流补偿电压信号中引入的偏移电压的电荷单元格被读取。

68. 发明授权

US4949307A Circuit for sensing the state of matrix cells in MOS EPROM memories including an offset current generator 失效
标题翻译：用于感测包括偏移电流发生器在内的MOS EPROM存储器中的矩阵单元的状态的电路
公开(公告)号：US4949307A
公开(公告)日：1990-08-14
申请号：US298487
申请日：1989-01-18
申请人： Giovanni Campardo
发明人： Giovanni Campardo
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , H03K19/177
CPC分类号： G11C16/28
摘要： The matrix cells and a virgin reference cell have their respective drains connected to a supply voltage through respective identical loads; a selection voltage is applied to the gate of a chosen matrix cell and to the gate of the virgin reference cell and the respective currents flowing across the two cells are compared in a differential amplifier. According to the invention, a generator is connected to the node between the drain of the reference cell and the voltage supply, and generates an offset current which is substantially constant as the supply voltage varies.

69. 发明授权

US4874965A Circuital device for the power-on reset of digital integrated circuits in MOS technology 失效
标题翻译： MOS技术中数字集成电路上电复位的电路设备
公开(公告)号：US4874965A
公开(公告)日：1989-10-17
申请号：US125344
申请日：1987-11-25
申请人： Giovanni Campardo , David Novosel
发明人： Giovanni Campardo , David Novosel
IPC分类号： H03K3/356 , H03K17/22
CPC分类号： H03K17/223 , H03K3/356008
摘要： A power-on reset circuit for supplying a reset pulse when a supply voltage rises above a preset threshold includes a reference voltage generator connected between the supply voltage and ground for supplying a reference signal having a constant preset value when the supply voltage is greater than the preset threshold. A supply follower provides an input signal which follows the supply voltage with a preset reduction factor. A bistable comparator having a first input driven by the reference signal and a second input driven by the input signal switches from a first state to a second state when the input signal exceeds the reference signal.
摘要翻译：当电源电压上升到预设阈值以上时提供复位脉冲的上电复位电路包括连接在电源电压和地之间的参考电压发生器，用于当电源电压大于所述电源电压时提供具有恒定预设值的参考信号预设阈值。电源跟随器以预设的减小因数提供跟随电源电压的输入信号。具有由参考信号驱动的第一输入和由输入信号驱动的第二输入的双稳态比较器在输入信号超过参考信号时从第一状态切换到第二状态。

70. 发明授权

US08228684B2 Multi chip electronic system 有权
标题翻译：多芯片电子系统
公开(公告)号：US08228684B2
公开(公告)日：2012-07-24
申请号：US12116852
申请日：2008-05-07
申请人： Aldo Losavio , Giovanni Campardo , Stefano Ricciardi
发明人： Aldo Losavio , Giovanni Campardo , Stefano Ricciardi
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06596 , H01L2924/01019 , H01L2924/13091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.
摘要翻译：一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成当第一和第二芯片叠加时相应的多个芯片间电连接。

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