专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06396168B2 Programmable logic arrays 有权
标题翻译：可编程逻辑阵列
公开(公告)号：US06396168B2
公开(公告)日：2002-05-28
申请号：US09782173
申请日：2001-02-12
申请人： Stefano Ghezzi , Donato Ferrario , Emilio Yero , Giovanni Campardo
发明人： Stefano Ghezzi , Donato Ferrario , Emilio Yero , Giovanni Campardo
IPC分类号： H03K19096
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1778 , Y10T307/505
摘要： A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.
摘要翻译：可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。属于同一列的晶体管可以彼此串联连接。串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。

2. 发明授权

US6069837A Row decoder circuit for an electronic memory device, particularly for low voltage applications 有权
标题翻译：用于电子存储器件的行解码器电路，特别是用于低电压应用
公开(公告)号：US6069837A
公开(公告)日：2000-05-30
申请号：US222022
申请日：1998-12-29
申请人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Stefano Ghezzi
发明人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Stefano Ghezzi
IPC分类号： G11C16/06 , G11C8/08 , G11C11/408 , G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, is described. The row decoding circuit is adapted to boost, through at least one boost capacitor, a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference and a second ground potential reference, and comprises a hierarchic structure of cascade connected inverters and a circuit means of progressively raising the read voltage level dynamically. First means are provided for raising the read voltage level to a value equal to the supply voltage plus a threshold voltage, and second means are provided for raising the read voltage level to a value equal to the supply voltage plus twice said threshold voltage.
摘要翻译：描述了用于电子存储单元装置的行解码电路，特别是在低电压应用中。行解码电路适于通过至少一个升压电容器升高要施加到包含要读取的存储器单元的存储器列的读取电压。电路在第一电源参考电压和第二接地电位基准之间供电，并且包括级联连接的反相器的分级结构和逐渐提高读取电压电平的电路装置。提供了用于将读取电压电平升高到等于电源电压加上阈值电压的值的第一装置，并且提供第二装置，用于将读取电压电平升高到等于电源电压加上两倍阈值电压的值。

3. 发明授权

US06169423A Method and circuit for regulating the length of an ATD pulse signal 有权
标题翻译：用于调节ATD脉冲信号长度的方法和电路
公开(公告)号：US06169423A
公开(公告)日：2001-01-02
申请号：US09186496
申请日：1998-11-04
申请人： Giovanni Campardo , Rino Micheloni , Matteo Zammattio , Donato Ferrario
发明人： Giovanni Campardo , Rino Micheloni , Matteo Zammattio , Donato Ferrario
IPC分类号： H03K522
CPC分类号： G11C8/18
摘要： The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.
摘要翻译：本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便还产生到读出放大器的均衡信号（SAEQ）。当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。

4. 发明授权

US6144589A Boosting circuit, particularly for a memory device 有权
标题翻译：升压电路，特别是用于存储器件
公开(公告)号：US6144589A
公开(公告)日：2000-11-07
申请号：US186758
申请日：1998-11-05
申请人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Carla Maria Golla
发明人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Carla Maria Golla
IPC分类号： G11C8/08 , G11C8/10 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10
摘要： A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.
摘要翻译：由第一电压电平和第二电压电平提供的升压电路，并具有能够获得第三电压电平的输出线，所述电路具有用于产生第三电压电平的至少两个不同的电路，所述至少两个电路可选择地激活用于产生第三电压电平并选择性地耦合到输出线。

5. 发明授权

US06286086B1 Data protection method for a semiconductor memory and corresponding protected memory device 失效
标题翻译：半导体存储器和相应的受保护存储器件的数据保护方法
公开(公告)号：US06286086B1
公开(公告)日：2001-09-04
申请号：US09220127
申请日：1998-12-23
申请人： Giovanni Campardo , Stefano Ghezzi , Giuseppe Giannini , Piero Enrico Torricelli
发明人： Giovanni Campardo , Stefano Ghezzi , Giuseppe Giannini , Piero Enrico Torricelli
IPC分类号： G06F1214
CPC分类号： G07F7/1008 , G06F12/1433 , G06F21/79 , G06Q20/341 , G06Q20/357 , G11C8/20 , G11C16/22
摘要： A method of protecting data in a semiconductor electronic memory, which includes using a protected memory portion within the matrix and respective dedicated decoding portions for storing, into the protected portion, a protection code without the address area of the matrix. The protection code can only be written and/or read through a command interpreter.
摘要翻译：一种保护半导体电子存储器中的数据的方法，其包括在矩阵内使用受保护的存储器部分和各个专用解码部分，用于将保护代码存储在保护部分中，而没有矩阵的地址区域。保护代码只能通过命令解释器进行写入和/或读取。

6. 发明授权

US6151251A Memory cell integrated structure with corresponding biasing device 有权
标题翻译：存储单元集成结构与相应的偏置装置
公开(公告)号：US6151251A
公开(公告)日：2000-11-21
申请号：US295667
申请日：1999-04-21
申请人： Giovanni Campardo , Stefano Zanardi , Maurizio Branchetti , Stefano Ghezzi
发明人： Giovanni Campardo , Stefano Zanardi , Maurizio Branchetti , Stefano Ghezzi
IPC分类号： G05F3/20 , H01L27/115 , G11C11/34
CPC分类号： H01L27/115 , G05F3/205
摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.
摘要翻译：一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管，连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制输出节点的电压范围。

7. 发明授权

US06304490B1 Memory cell integrated structure with corresponding biasing device 失效
标题翻译：存储单元集成结构与相应的偏置装置
公开(公告)号：US06304490B1
公开(公告)日：2001-10-16
申请号：US09675985
申请日：2000-09-29
申请人： Giovanni Campardo , Stefano Zanardi , Maurizio Branchetti , Stefano Ghezzi
发明人： Giovanni Campardo , Stefano Zanardi , Maurizio Branchetti , Stefano Ghezzi
IPC分类号： G11C1134
CPC分类号： H01L27/115 , G05F3/205
摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.
摘要翻译：一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管，连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制输出节点的电压范围。

8. 发明授权

US5923076A Integrated device with pads 失效
标题翻译：集成器件与焊盘
公开(公告)号：US5923076A
公开(公告)日：1999-07-13
申请号：US811577
申请日：1997-03-05
申请人： Giovanni Campardo , Matteo Zammattio , Stefano Ghezzi
发明人： Giovanni Campardo , Matteo Zammattio , Stefano Ghezzi
IPC分类号： H01L23/485 , H01L29/78
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.
摘要翻译：具有形成在P型衬底中的N型阱区和容纳在阱区中的N +型接触环的集成器件。阱区形成具有叠加在衬底上的导电层以及衬底本身的各个电容器。导电层和基板接地，接触环连接到电源，使得两个电容器彼此平行，并且与阱区域的内部电阻一起形成用于稳定电源电压的滤波器。当连接到器件的输入缓冲级时，滤波器通过输出缓冲器的高电流切换来提供阻尼输入缓冲器电源线上产生的峰值。

9. 发明授权

US08958242B2 Thermal treatment of flash memories 有权
标题翻译：闪存的热处理
公开(公告)号：US08958242B2
公开(公告)日：2015-02-17
申请号：US13101322
申请日：2011-05-05
申请人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
发明人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
IPC分类号： G11C11/34 , H05B3/00 , G11C11/00 , G11C16/34 , H01L23/34
CPC分类号： G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
摘要翻译：存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。如果需要，加热后，可以刷新存储器。在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

10. 发明申请

US20140015560A1 INTERFACE BOARD OF A TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES AND CORRESPONDING PROBE HEAD 有权
标题翻译：用于电子设备测试设备和相关探头的测试头接口板
公开(公告)号：US20140015560A1
公开(公告)日：2014-01-16
申请号：US13548004
申请日：2012-07-12
申请人： Giovanni Campardo , Flavio Maggioni , Riccardo Liberini
发明人： Giovanni Campardo , Flavio Maggioni , Riccardo Liberini
IPC分类号： G01R1/073
CPC分类号： G01R1/07378
摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.
摘要翻译：描述了用于电子设备的测试设备的测试头的接口板。测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式