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61. 发明授权

US06849481B1 Thyristor-based SRAM and method for the fabrication thereof 失效
标题翻译：基于晶闸管的SRAM及其制造方法
公开(公告)号：US06849481B1
公开(公告)日：2005-02-01
申请号：US10628912
申请日：2003-07-28
申请人： Elgin Quek , Pradeep Ramachandramurthy Yelehanka , Jia Zhen Zheng , Tommy Lai , Weining Li
发明人： Elgin Quek , Pradeep Ramachandramurthy Yelehanka , Jia Zhen Zheng , Tommy Lai , Weining Li
IPC分类号： H01L21/332 , H01L21/8244 , H01L27/11
CPC分类号： H01L29/66393 , H01L27/11
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.
摘要翻译：一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。晶闸管具有至少四层，其间具有三个P-N结。至少两层是水平形成的，并且至少两层是垂直形成的。在至少一个垂直形成的层之间形成栅极。在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

62. 发明授权

US06610575B1 Forming dual gate oxide thickness on vertical transistors by ion implantation 有权
标题翻译：通过离子注入在垂直晶体管上形成双栅氧化层厚度
公开(公告)号：US06610575B1
公开(公告)日：2003-08-26
申请号：US10161818
申请日：2002-06-04
申请人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L218234
CPC分类号： H01L21/823857 , H01L21/823885
摘要： A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the non-modified surfaces of the at least one of the non-doped outer or inner side walls.
摘要翻译：一种具有双栅极氧化物厚度的结构的方法，包括以下步骤。提供具有第一和第二柱的衬底。第一和第二支柱各自具有外侧壁和内侧壁。至少一个第一和第二支柱的外侧壁或内侧壁中的至少一个被遮蔽，留下第一和第二柱中的至少一个的至少一个外壁或内侧壁暴露。然后通过暴露的外侧壁或内侧壁中的至少一个植入掺杂剂，改变掺杂的暴露的外壁或内侧壁中的至少一个的表面。第一和第二支柱中的至少一个的被掩蔽的外侧壁或内侧壁中的至少一个被遮蔽。栅极氧化物生长在第一和第二柱的外侧壁和内侧壁上，其中生长在掺杂的外壁或内侧壁中的至少一个的改性表面上的栅极氧化物比生长在栅极氧化物上的栅极氧化物厚所述非掺杂外侧壁或内侧壁中的至少一个的未修饰表面。

63. 发明授权

US06541327B1 Method to form self-aligned source/drain CMOS device on insulated staircase oxide 失效
标题翻译：在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
公开(公告)号：US06541327B1
公开(公告)日：2003-04-01
申请号：US09760123
申请日：2001-01-16
申请人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L29/66492 , H01L21/823814 , H01L29/41783 , H01L29/665 , H01L29/66575
摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
摘要翻译：一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。栅极结构形成在衬底上。栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。在衬底和栅极结构之上形成第一绝缘层。形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。我们通过抗蚀剂层中的开口蚀刻绝缘层。蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。在栅电极，绝缘层上沉积导电层。导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

64. 发明授权

US06436770B1 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation 失效
标题翻译：通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法
公开(公告)号：US06436770B1
公开(公告)日：2002-08-20
申请号：US09721720
申请日：2000-11-27
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L21332
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/66666
摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
摘要翻译：一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。在衬底中形成隔离区。隔离区限定有效区域。然后，我们在活动区域中形成一个源区域。在有源区域和隔离区域上形成介电层。我们在电介质层上形成阻挡层。我们在屏障层形成一个开口。在开口中形成栅极层。我们在导电层和阻挡层上形成绝缘层。我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。栅极电介质隔离物形成在栅极层的侧壁上。然后，我们形成一个填充门开口的导电塞。绝缘层被去除。我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。导电插塞的其余部分包括沟道区域。沟道长度在源极区域的顶部和漏极区域之间。我们在阻挡层，栅极层和导电插塞上形成层间电介质层。通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。

65. 发明授权

US06313008B1 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon 失效
标题翻译：使用微加工技术形成气球形STI以去除重掺杂硅的方法
公开(公告)号：US06313008B1
公开(公告)日：2001-11-06
申请号：US09768486
申请日：2001-01-25
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.
摘要翻译：本发明描述了形成球形STI沟槽的方法的三个实施例。第一实施例开始于在衬底上形成阻挡层。在阻挡层中形成隔离开口。接下来，通过所述隔离开口将离子注入到所述衬底中，以形成Si损伤或掺杂的第一区域。第一区域是选择性蚀刻以形成孔。孔用绝缘材料填充以形成气球形的浅沟槽隔离（STI）区域。衬底在所述球形浅沟槽隔离（STI）区域之间具有有效区域。第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。在通过沟槽对衬底进行各向同性蚀刻之前，第三实施例在沟槽中形成衬垫。

66. 发明授权

US08785287B2 Method to tune narrow width effect with raised S/D structure 有权
标题翻译：用提高的S / D结构调整窄宽度效应的方法
公开(公告)号：US08785287B2
公开(公告)日：2014-07-22
申请号：US12803754
申请日：2010-07-06
申请人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
发明人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L27/088 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/41783 , H01L29/6659 , H01L29/7848
摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
摘要翻译：制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

67. 发明授权

US08288800B2 Hybrid transistor 有权
标题翻译：混合晶体管
公开(公告)号：US08288800B2
公开(公告)日：2012-10-16
申请号：US12651487
申请日：2010-01-04
申请人： Ming Zhu , Chun Shan Yin , Elgin Quek , Shyue Seng Tan
发明人： Ming Zhu , Chun Shan Yin , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L29/66
CPC分类号： H01L29/7885 , H01L21/28273 , H01L29/66795 , H01L29/66825 , H01L29/785
摘要： A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
摘要翻译：公开了一种形成装置的方法。该方法包括提供具有活性区域的基底。在基板上形成栅极。形成通过栅极的第一和第二电流路径。第一电流通路用于第一目的，第二电流通路用于第二目的。门控制当前路径的选择。

68. 发明申请

US20070132032A1 Selective stress relaxation of contact etch stop layer through layout design 有权
标题翻译：通过布局设计，接触蚀刻停止层的选择性应力松弛
公开(公告)号：US20070132032A1
公开(公告)日：2007-06-14
申请号：US11302035
申请日：2005-12-13
申请人： Lee Teo , Elgin Quek , Dong Sohn
发明人： Lee Teo , Elgin Quek , Dong Sohn
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76829 , H01L21/823814 , H01L21/823871 , H01L27/0207 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.
摘要翻译：一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

69. 发明申请

US20070117326A1 MATERIAL ARCHITECTURE FOR THE FABRICATION OF LOW TEMPERATURE TRANSISTOR 审中-公开
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20070117326A1
公开(公告)日：2007-05-24
申请号：US11625789
申请日：2007-01-22
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083 , H01L29/6659
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

70. 发明申请

US20060006427A1 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20060006427A1
公开(公告)日：2006-01-12
申请号：US10886442
申请日：2004-07-07
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

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