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61. 发明授权

US08549264B2 Add instructions to add three source operands 有权
标题翻译：添加指令以添加三个源操作数
公开(公告)号：US08549264B2
公开(公告)日：2013-10-01
申请号：US12645334
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3001 , G06F9/30094
摘要： A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收添加指令。加法指令可以指示第一源操作数，第二源操作数和第三源操作数。作为加法指令的结果，可以存储第一，第二和第三源操作数的总和。该和可以部分地存储在由加法指令指示的目的地操作数中，部分地存储在多个标志中。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

62. 发明申请

US20130227252A1 Add Instructions to Add Three Source Operands 有权
标题翻译：添加说明来添加三个源操作数
公开(公告)号：US20130227252A1
公开(公告)日：2013-08-29
申请号：US13802540
申请日：2013-03-13
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30094
摘要： A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收添加指令。加法指令可以指示第一源操作数，第二源操作数和第三源操作数。作为加法指令的结果，可以存储第一，第二和第三源操作数的总和。该和可以部分地存储在由加法指令指示的目的地操作数中，部分地存储在多个标志中。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

63. 发明授权

US08402252B2 Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode 有权
标题翻译：用三字节转义操作码来排除指令特定操作码的地址格式字段的指令长度
公开(公告)号：US08402252B2
公开(公告)日：2013-03-19
申请号：US13417241
申请日：2012-03-10
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

64. 发明申请

US20110161635A1 Rotate instructions that complete execution without reading carry flag 有权
标题翻译：旋转完成执行的指令，无需读取进位标志
公开(公告)号：US20110161635A1
公开(公告)日：2011-06-30
申请号：US12655213
申请日：2009-12-26
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
摘要翻译：一个方面的方法可以包括接收旋转指令。旋转指令可以指示源操作数和旋转量。结果可以存储在由旋转指令指示的目标操作数中。结果可能使源操作数旋转了旋转量。旋转指令的执行可以在不读取进位标志的情况下完成。

65. 发明申请

US20110153994A1 Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag 有权
标题翻译：执行完成的乘法指令不写入进位标志
公开(公告)号：US20110153994A1
公开(公告)日：2011-06-23
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdinc Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdinc Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F9/302
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收乘法指令。乘法指令可以指示第一源操作数和第二源操作数。第一和第二源操作数的乘积可以存储在由乘法指令指示的一个或多个目的地操作数中。乘法指令的执行可以在不写进位标志的情况下完成。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

66. 发明授权

US07941651B1 Method and apparatus for combining micro-operations to process immediate data 有权
标题翻译：用于组合微操作以处理即时数据的方法和装置
公开(公告)号：US07941651B1
公开(公告)日：2011-05-10
申请号：US10185876
申请日：2002-06-27
申请人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
发明人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
IPC分类号： G06F9/34
CPC分类号： G06F9/3001 , G06F9/30003 , G06F9/30145 , G06F9/30167 , G06F9/3017
摘要： A method and apparatus for combining micro-operations to process immediate data. The immediate data may be wider than the immediate data storage capacity of a micro-operation. A first micro-operation is issued to process a first portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. A second micro-operation is issued to process a second portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. Execution of the first and second micro-operations and optionally of a third micro-operation serves to reconstruct the immediate data comprising the first portion and the second portion of the immediate data.
摘要翻译：一种用于组合微操作以处理即时数据的方法和装置。即时数据可能比微操作的即时数据存储容量更宽。发出第一微操作以处理即时数据的第一部分，其可以在微操作的即时数据存储容量内处理。发出第二微操作以处理立即数据的第二部分，其可以在微操作的即时数据存储容量内处理。执行第一和第二微操作以及可选地第三微操作用于重构包括即时数据的第一部分和第二部分的即时数据。

67. 发明授权

US06308279B1 Method and apparatus for power mode transition in a multi-thread processor 失效
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06308279B1
公开(公告)日：2001-10-23
申请号：US09083281
申请日：1998-05-22
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F126
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

68. 发明授权

US09268596B2 Instruction and logic to test transactional execution status 有权
标题翻译：测试事务执行状态的指令和逻辑
公开(公告)号：US09268596B2
公开(公告)日：2016-02-23
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

69. 发明申请

US20150186140A1 OPCODE TRAPPING 审中-公开
标题翻译：操作码捕捉
公开(公告)号：US20150186140A1
公开(公告)日：2015-07-02
申请号：US14142835
申请日：2013-12-28
申请人： Bret L. Toll , Buford M. Guy , Ronak Singhal , Glenn J. Hinton , Mishali Naik
发明人： Bret L. Toll , Buford M. Guy , Ronak Singhal , Glenn J. Hinton , Mishali Naik
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3861
摘要： Embodiments of an invention for opcode trapping are disclosed. In one embodiment, a processor includes an instruction unit to receive an instruction, the instruction unit having a match storage location in which to store a match value and a comparator. The comparator is to compare the match value to a portion of the instruction. Control of the processor is to be transferred to a trap handler if the comparator indicates that the match value matches the portion of the instruction.
摘要翻译：公开了用于操作码捕获的发明的实施例。在一个实施例中，处理器包括用于接收指令的指令单元，所述指令单元具有存储匹配值的匹配存储位置和比较器。比较器将匹配值与指令的一部分进行比较。如果比较器指示匹配值与指令的部分匹配，则将处理器的控制传送到陷阱处理程序。

70. 发明申请

US20140281236A1 SYSTEMS AND METHODS FOR IMPLEMENTING TRANSACTIONAL MEMORY 审中-公开
标题翻译：用于实现交易记忆的系统和方法
公开(公告)号：US20140281236A1
公开(公告)日：2014-09-18
申请号：US13803658
申请日：2013-03-14
申请人： William C. Rash , Scott D. Hahn , Bret L. Toll , Glenn J. Hinton
发明人： William C. Rash , Scott D. Hahn , Bret L. Toll , Glenn J. Hinton
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F9/467
摘要： Systems and methods for implementing transactional memory access. An example method may comprise initiating a memory access transaction; executing a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, and/or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location; executing a non-transactional read operation with respect to a third memory location, and/or a non-transactional write operation with respect to a fourth memory location; responsive to detecting, by the memory access tracking logic, access by a device other than the processor to the first memory location or the second memory location, aborting the memory access transaction; and completing, irrespectively of the state of the third memory location and the fourth memory location, the memory access transaction responsive to failing to detect a transaction aborting condition.
摘要翻译：用于实现事务性存储器访问的系统和方法。示例性方法可以包括启动存储器访问事务; 执行事务读取操作，使用与存储器访问跟踪逻辑相关联的与存储器访问跟踪逻辑相关联的第一缓冲器相对于第一存储器位置和/或事务写入操作，使用与存储器访问跟踪逻辑相关联的第二缓冲器第二存储器位置; 执行关于第三存储器位置的非事务性读取操作和/或关于第四存储器位置的非事务写操作; 响应于通过存储器访问跟踪逻辑检测由处理器之外的设备到第一存储器位置或第二存储器位置的访问，中止存储器访问事务; 并且与第三存储器位置和第四存储器位置的状态无关地完成，存储器访问事务响应于不能检测到事务中止条件。

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