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1. 发明授权

US07181597B2 Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module 失效
标题翻译：解码指令，用于跟踪缓存恢复状态，系统将解码的操作传递到跟踪缓存和执行分配模块
公开(公告)号：US07181597B2
公开(公告)日：2007-02-20
申请号：US11217707
申请日：2005-08-31
申请人： John Alan Miller , Stephan Jourdan
发明人： John Alan Miller , Stephan Jourdan
IPC分类号： G06F9/06
CPC分类号： G06F9/3808 , G06F9/3824 , G06F9/3826
摘要： A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.
摘要翻译：管理处理器指令的系统和方法提供增强的性能。该系统和方法提供用解码器将第一指令解码为多个操作。操作的第一个副本从解码器传递到与跟踪缓存相关联的构建引擎。该系统和方法进一步提供将操作的第二副本从解码器直接传递到后端分配模块，使得操作绕过构建引擎并且分配模块处于解码器读取状态。

2. 发明授权

US07913064B2 Operation frame filtering, building, and execution 有权
标题翻译：操作框架过滤，构建和执行
公开(公告)号：US07913064B2
公开(公告)日：2011-03-22
申请号：US12413650
申请日：2009-03-30
申请人： Stephan Jourdan , Per Hammarlund , Alexandre Farcy , John Alan Miller
发明人： Stephan Jourdan , Per Hammarlund , Alexandre Farcy , John Alan Miller
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3802
摘要： The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.
摘要翻译：本主题涉及操作框架过滤，构建和执行。一些实施例包括识别帧签名，计数帧签名的执行次数，以及构建要执行的操作帧，而不是由帧签名识别的操作。

3. 发明申请

US20090187712A1 Operation Frame Filtering, Building, And Execution 有权
标题翻译：操作框架过滤，构建和执行
公开(公告)号：US20090187712A1
公开(公告)日：2009-07-23
申请号：US12413650
申请日：2009-03-30
申请人： Stephan Jourdan , Per Hammarlund , Alexandre Farcy , John Alan Miller
发明人： Stephan Jourdan , Per Hammarlund , Alexandre Farcy , John Alan Miller
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F9/3802
摘要： The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.
摘要翻译：本主题涉及操作框架过滤，构建和执行。一些实施例包括识别帧签名，计数帧签名的执行次数，以及构建要执行的操作帧，而不是由帧签名识别的操作。

4. 发明授权

US07143273B2 Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history 失效
标题翻译：用于利用多种炖制算法对全球历史进行索引的动态分支预测的方法和装置
公开(公告)号：US07143273B2
公开(公告)日：2006-11-28
申请号：US10404812
申请日：2003-03-31
申请人： John Alan Miller , Slade A. Morgan , Stephan J. Jourdan
发明人： John Alan Miller , Slade A. Morgan , Stephan J. Jourdan
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3808 , G06F9/3848
摘要： Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.
摘要翻译：在从跟踪高速缓存中读取跟踪并且可重复访问全局历史记录中访问跟踪高速缓存中的指令的排序所暗示的由分支预测创建的炖菜时，切换全局历史记录中的条目读取跟踪高速缓冲存储器内的跟踪内的分支指令多于一条第二分支指令时，炖菜的变化。

5. 发明授权

US07941651B1 Method and apparatus for combining micro-operations to process immediate data 有权
标题翻译：用于组合微操作以处理即时数据的方法和装置
公开(公告)号：US07941651B1
公开(公告)日：2011-05-10
申请号：US10185876
申请日：2002-06-27
申请人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
发明人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
IPC分类号： G06F9/34
CPC分类号： G06F9/3001 , G06F9/30003 , G06F9/30145 , G06F9/30167 , G06F9/3017
摘要： A method and apparatus for combining micro-operations to process immediate data. The immediate data may be wider than the immediate data storage capacity of a micro-operation. A first micro-operation is issued to process a first portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. A second micro-operation is issued to process a second portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. Execution of the first and second micro-operations and optionally of a third micro-operation serves to reconstruct the immediate data comprising the first portion and the second portion of the immediate data.
摘要翻译：一种用于组合微操作以处理即时数据的方法和装置。即时数据可能比微操作的即时数据存储容量更宽。发出第一微操作以处理即时数据的第一部分，其可以在微操作的即时数据存储容量内处理。发出第二微操作以处理立即数据的第二部分，其可以在微操作的即时数据存储容量内处理。执行第一和第二微操作以及可选地第三微操作用于重构包括即时数据的第一部分和第二部分的即时数据。

6. 发明授权

US06954849B2 Method and system to use and maintain a return buffer 失效
标题翻译：方法和系统使用和维护一个返回缓冲区
公开(公告)号：US06954849B2
公开(公告)日：2005-10-11
申请号：US10081053
申请日：2002-02-21
申请人： John Alan Miller , Michael J. St. Clair
发明人： John Alan Miller , Michael J. St. Clair
IPC分类号： G06F9/00 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/40 , G06F9/42 , G06F9/54 , G06F15/00 , G06F15/163
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction was detected by a second pipeline and will send the return address to the second pipeline if the call was not detected by the second pipeline. Upon detecting a return instruction, the pipeline will pop the return address at the top of its return buffer. The return address may then be used in the instruction pipeline. The pipeline will send a request to a third pipeline to fill its return buffer with entries from the third pipeline's return buffer. The pipeline will determine if the return instruction was detected by a second pipeline and will send the return address at the top of its return buffer to the second pipeline if the return was not detected by the second pipeline.
摘要翻译：微处理器中的指令流水线包括保持返回缓冲器的一条或多条管道。在检测到呼叫指令时，流水线将返回地址推送到其返回缓冲区。然后，管道将确定呼叫指令是否被第二管道检测到，并且如果第二管道没有检测到呼叫，则将返回地址发送到第二管道。检测到返回指令后，管道将弹出返回缓冲区顶部的返回地址。然后可以在指令流水线中使用返回地址。流水线将向第三条流水线发送请求，以从第三条流水线的返回缓冲区中输入条目来填充其返回缓冲区。流水线将确定返回指令是否被第二个流水线检测到，并且如果第二个管道没有检测到返回，并且将其返回缓冲区顶部的返回地址发送到第二个管道。

7. 发明授权

US06898699B2 Return address stack including speculative return address buffer with back pointers 失效
标题翻译：返回地址堆栈，包括具有后向指针的推测返回地址缓冲区
公开(公告)号：US06898699B2
公开(公告)日：2005-05-24
申请号：US10029128
申请日：2001-12-21
申请人： Stephan J. Jourdan , John Alan Miller , Namratha Jaisimha
发明人： Stephan J. Jourdan , John Alan Miller , Namratha Jaisimha
IPC分类号： G06F9/00 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3808 , G06F9/30054 , G06F9/3802 , G06F9/3806 , G06F9/3842 , G06F9/3848
摘要： An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.
摘要翻译：一种用于存储由流水线处理器执行的指令的预测返回地址的装置，该装置包括两部分返回地址缓冲器，其包括推测返回地址缓冲器和承诺返回地址缓冲器，两者都具有可包括预测返回的多个条目被推送到返回缓冲区的地址。

8. 发明授权

US07533247B2 Operation frame filtering, building, and execution 失效
标题翻译：操作框架过滤，构建和执行
公开(公告)号：US07533247B2
公开(公告)日：2009-05-12
申请号：US11324143
申请日：2005-12-30
申请人： Stephan Jourdan , Per Hammarlund , Alexandre Farcy , John Alan Miller
发明人： Stephan Jourdan , Per Hammarlund , Alexandre Farcy , John Alan Miller
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3802
摘要： The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.
摘要翻译：本主题涉及操作框架过滤，构建和执行。一些实施例包括识别帧签名，计数帧签名的执行次数，以及构建要执行的操作帧，而不是由帧签名识别的操作。

9. 发明授权

US07181598B2 Prediction of load-store dependencies in a processing agent 失效
标题翻译：预处理代理中的加载存储依赖关系
公开(公告)号：US07181598B2
公开(公告)日：2007-02-20
申请号：US10146956
申请日：2002-05-17
申请人： Stephan J. Jourdan , Darrell D. Boggs , John Alan Miller , Ronak Singhal
发明人： Stephan J. Jourdan , Darrell D. Boggs , John Alan Miller , Ronak Singhal
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3857
摘要： In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.
摘要翻译：在处理核心中，新接收的加载指令可以取决于先前接收的存储指令。核心可以包括预测这种依赖性的预测器，并提供碰撞存储指令的标识。加载指令可以存储在具有依赖标记的调度器中。此后，可以防止加载指令在执行冲突存储之前执行。在执行负载时，确认预测的精度。在加载指令退出后，可以向预测器提供新的预测结果。

10. 发明授权

US07103751B1 Method and apparatus for representation of an address in canonical form 有权
标题翻译：以规范形式表示地址的方法和装置
公开(公告)号：US07103751B1
公开(公告)日：2006-09-05
申请号：US10186004
申请日：2002-06-27
申请人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
发明人： Bret L. Toll , John Alan Miller , Michael A. Fetterman
IPC分类号： G06F12/00
CPC分类号： G06F12/0615
摘要： A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical form. The error indicator is stored together with a portion of the address, the portion being less than the entire address. The error indicator, together with the portion of the address stored, represent the address received.
摘要翻译：一种用于以规范形式表示地址的方法和装置。接收地址，并根据地址是否以正确的规范形式接收，计算错误指示符。错误指示器与地址的一部分一起存储，该部分小于整个地址。错误指示器与存储的地址部分一起表示收到的地址。

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