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61. 发明授权

US5455931A Programmable clock tuning system and method 失效
标题翻译：可编程时钟调谐系统及方法
公开(公告)号：US5455931A
公开(公告)日：1995-10-03
申请号：US155178
申请日：1993-11-19
申请人： Peter J. Camporese , Patrick J. Meaney , Brian J. O'Leary , Richard F. Rizzolo
发明人： Peter J. Camporese , Patrick J. Meaney , Brian J. O'Leary , Richard F. Rizzolo
IPC分类号： G06F1/10 , G06F17/50 , G06F1/04
CPC分类号： G06F17/5031 , G06F1/10
摘要： A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.
摘要翻译：一种具有增强的定时故障诊断和非层次功能的数据处理系统的时钟调整系统和方法。通用和单独的相位调整功能均可确保分布在计算机系统中的时钟脉冲的可编程调谐，从而便于通过在逻辑路径之间移动时序余量来将定时裕度故障隔离到特定的时钟信号或增强系统性能。讨论了单时钟和双时钟数据处理以及每个时钟调整实施例。

62. 发明申请

US20130339822A1 BAD WORDLINE/ARRAY DETECTION IN MEMORY 有权
公开(公告)号：US20130339822A1
公开(公告)日：2013-12-19
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

63. 发明申请

US20130339811A1 BITLINE DELETION 有权
公开(公告)号：US20130339811A1
公开(公告)日：2013-12-19
申请号：US13523624
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/1064 , G06F12/0802 , G11C29/702 , G11C2029/0409 , G11C2029/0411 , G11C2029/1204
摘要： Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.
摘要翻译：基于在所选择的位线地址检测高速缓存中的高位线错误率条件，其中高位线错误率条件指示所选位线地址处的高错误率，激活可编程切换缓存。该方法还包括基于可编程开关被激活并遇到与所选择的位线地址相关联的错误，由计算机系统自动地删除与高速缓存中的后续错误相关联的一个或多个高速缓存行，而不管随后的地址如何基于激活的可编程开关的错误，其中自动线删除指示线不可用。

64. 发明授权

US08122297B2 Method and apparatus for parallel and serial data transfer 有权
标题翻译：并行和串行数据传输的方法和装置
公开(公告)号：US08122297B2
公开(公告)日：2012-02-21
申请号：US11874232
申请日：2007-10-18
申请人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
发明人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).
摘要翻译：公开了一种用于在通过系统传送的地址，数据和控制的系统中进行维护操作的方法和装置，允许并行和串行操作共存，而并行操作不被串行操作减慢。它还提供了常用的移位器，引擎和协议的使用，以及系统中根据需要将ECC高效地转换为奇偶校验和奇偶校验。本发明还提供了本地和报告状态的错误检测和隔离。本发明提供大的维护地址和数据空间（通常支持64位地址和64位数据）。

65. 发明申请

US20110320732A1 USER-CONTROLLED TARGETED CACHE PURGE 失效
标题翻译：用户控制的高速缓存池
公开(公告)号：US20110320732A1
公开(公告)日：2011-12-29
申请号：US12822428
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/126
摘要： User-controlled targeted cache purging includes receiving a request to perform an operation to purge data from a cache, the request including an index identifier identifying an index associated with the cache. The index specifies a portion of the cache to be purged. The user-controlled targeted cache purging also includes purging the data from the cache, and providing notification of successful completion of the operation.
摘要翻译：用户控制的目标缓存清除包括接收执行从缓存清除数据的操作的请求，所述请求包括标识与高速缓存相关联的索引的索引标识符。该索引指定要清除的缓存的一部分。用户控制的目标缓存清除还包括从缓存中清除数据，并提供成功完成操作的通知。

66. 发明授权

US07882322B2 Early directory access of a double data rate elastic interface 失效
标题翻译：早期目录访问的双倍数据速率弹性界面
公开(公告)号：US07882322B2
公开(公告)日：2011-02-01
申请号：US11426675
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译：一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。有很多应用程序。在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。

67. 发明授权

US07752475B2 Late data launch for a double data rate elastic interface 失效
标题翻译：推迟数据速率的双倍数据速率弹性界面
公开(公告)号：US07752475B2
公开(公告)日：2010-07-06
申请号：US11426671
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译：双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。

68. 发明申请

US20080276024A1 Method for Stabilizing Asynchronous Interfaces 审中-公开
标题翻译：稳定异步接口的方法
公开(公告)号：US20080276024A1
公开(公告)日：2008-11-06
申请号：US12137600
申请日：2008-06-12
申请人： Patrick J. Meaney , Anthony P. Cullen , Michael Fee
发明人： Patrick J. Meaney , Anthony P. Cullen , Michael Fee
IPC分类号： G06F13/372 , G06F3/00
CPC分类号： G06F13/4226
摘要： A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.
摘要翻译：一种在不使用异步控制信号的情况下在源和宿之间进行异步数据传输的方法和计算机系统装置。包括亚稳态电路，数据变化检测逻辑，稳定窗口延迟计数器和多路复用器/寄存器对，以允许在转换期间保持先前的稳定数据。虽然采用的处理逻辑专门适用于异步逻辑，但逻辑也可以扩展到同步或未定义的接口。还公开了一种用于调整窗口延迟的可编程装置。

69. 发明授权

US07331027B2 Method for swapping circuits in a metal-only engineering change 失效
标题翻译：仅在金属工程变更中交换电路的方法
公开(公告)号：US07331027B2
公开(公告)日：2008-02-12
申请号：US10894664
申请日：2004-07-20
申请人： Patrick J. Meaney
发明人： Patrick J. Meaney
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045 , G06F2217/64
摘要： A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing violations, existing, non-filler books which are in close proximity are considered for swapping with the eco books. The book swaps are all done with wire connections only (i.e. the book placements are not affected). This way, critical paths and non-critical paths can be traded-off to achieve a faster design, even though books are not allowed to be moved. Some simple algorithms are discussed; however, there are many heuristic and analytic algorithms that can be applied in choosing swaps, based on the needs of the particular design.
摘要翻译：公开了一种在金属工程变更之后改进设计标准和重要的时间标准的方法。该方法包括进行新书（门级，填充单元电路，称为“生态书”）的初始逻辑更改，使用新书运行布局和路由，以及计算结果逻辑。如果存在时间违规，则认为与生态书籍进行交换的现有非填充书。书籍交换全部仅通过电线连接完成（即图书布置不受影响）。这样，关键路径和非关键路径可以被交换，以实现更快的设计，即使书籍不被允许移动。讨论了一些简单的算法; 然而，根据特定设计的需要，有许多启发式和分析算法可以应用于选择交换。

70. 发明授权

US07275224B2 Method for providing an area optimized binary orthogonality checker 失效
标题翻译：提供区域优化二进制正交检验器的方法
公开(公告)号：US07275224B2
公开(公告)日：2007-09-25
申请号：US10817279
申请日：2004-04-02
申请人： Patrick J. Meaney , Alan P. Wagstaff
发明人： Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F17/50 , H04J11/00 , G06F13/00 , G06F3/00 , G06F15/173
CPC分类号： G06F17/5045
摘要： A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is adaptable to various libraries of logical gates to implement the circuit and the area for each gate in the library. The optimal mix of hierarchical levels and stages is determined such that the orthogonality checker achieves the minimized circuit area. An orthogonality checker is employed in a scalable selector system for controlling data transfers and routing in a data processing system to allow. Combining orthogonality checking with existing selector hierarchically allows for the maximum reuse of circuits, signals, and proximity; thus potentially reducing wiring as well. Multiple hierarchical checks are used in favor of one large. This structure is extended to multiple hierarchical levels and works with orthogonality checks of any size or implementation. The invention also determines the optimal hierarchical structure for a given technology library and a given number of inputs to check. It can also be used within a flat hierarchy or macro as a technique to reduce circuits.
摘要翻译：一种用于最小化在静态CMOS电路中实现的二进制正交检验器的面积的方法，用于最小化检验器实现所需的门数和面积。该方法适用于逻辑门的各种库，以实现库中每个门的电路和区域。确定层次级别和级别的最佳组合，使得正交检验器实现最小化的电路面积。在可扩展选择器系统中采用正交检验器，用于在数据处理系统中控制数据传输和路由以允许。将正交检查与现有选择器分层组合允许电路，信号和接近度的最大重用; 从而潜在地减少布线。使用多层次检查有利于一个大型。该结构扩展到多个层次级别，并且可以与任何大小或实现的正交性检查一起工作。本发明还确定给定技术库的最优层次结构以及给定数量的输入以进行检查。它也可以在平面层级或宏中用作减少电路的技术。

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