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61. 发明授权

US06326794B1 Method and apparatus for in-situ monitoring of ion energy distribution for endpoint detection via capacitance measurement 失效
标题翻译：用于通过电容测量进行端点检测的离子能量分布的现场监测方法和装置
公开(公告)号：US06326794B1
公开(公告)日：2001-12-04
申请号：US09231043
申请日：1999-01-14
申请人： Paul Matthew Lundquist , Son Van Nguyen , Manmohanjit Singh
发明人： Paul Matthew Lundquist , Son Van Nguyen , Manmohanjit Singh
IPC分类号： G01R2726
CPC分类号： H01J37/32935 , G01N27/62 , G01R19/0061 , H01J37/32963
摘要： A method and apparatus that provides in-situ monitoring of both the ion flux and the ion energy distribution of plasma processes to determine the endpoint of the etch process or the integrity and reproducibility of the deposition process where ion bombardment and energy distribution play critical roles in the process. A capacitance sensor is provided for measuring ion flux and ion distribution. At least one capacitance sensor is disposed within a plasma reactor at a first position for detecting ion flux emanating from a plasma within the plasma reactor. The capacitance sensor generates an ion flux measurement signal in response to the detection of the ion flux. Each of the at least one capacitance sensors is coupled to signal lines for routing an ion flux measurement signal outside the plasma reactor. A plurality of capacitance sensors may be formed as one of a plurality of rows of parts to be processed.
摘要翻译：提供等离子体处理的离子通量和离子能量分布的原位监测的方法和装置，以确定蚀刻过程的终点或沉积过程的完整性和再现性，其中离子轰击和能量分布在的过程。提供电容传感器用于测量离子通量和离子分布。至少一个电容传感器设置在第一位置处的等离子体反应器内，用于检测从等离子体反应器内的等离子体发出的离子通量。电容传感器响应于离子通量的检测而产生离子通量测量信号。所述至少一个电容传感器中的每一个耦合到用于在等离子体反应器外部布置离子通量测量信号的信号线。多个电容传感器可以形成为要处理的多行零件之一。

62. 发明授权

US6051099A Apparatus for achieving etch rate uniformity 失效
标题翻译：用于实现蚀刻速率均匀性的装置
公开(公告)号：US6051099A
公开(公告)日：2000-04-18
申请号：US949720
申请日：1997-10-14
申请人： Raymond Bus-Kwoffie , Son Van Nguyen , Diana Perez , Andrew Chiuyan Ting , John Wesley Williams
发明人： Raymond Bus-Kwoffie , Son Van Nguyen , Diana Perez , Andrew Chiuyan Ting , John Wesley Williams
IPC分类号： H01J37/32 , H05H1/00
CPC分类号： H01J37/32633
摘要： A can for use in an etching system including a continuous conductive wall with a first opening to be placed adjacent the reactor upper electrode and a second opening to be placed adjacent the reactor lower electrode. Preferably, the conductive wall is a dual wall further including an inner wall and an outer wall, the inner and outer wall separated by one or more openings configured normal to the height of the continuous wall, the openings allowing for the flow of coolant through the wall.
摘要翻译：一种用于蚀刻系统的罐，包括具有邻近反应器上电极放置的第一开口的连续导电壁和邻近反应器下电极放置的第二开口。优选地，导电壁是还包括内壁和外壁的双壁，内壁和外壁由一个或多个开口构成，垂直于连续壁的高度，开口允许冷却剂流过壁。

63. 发明授权

US5973385A Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby 失效
公开(公告)号：US5973385A
公开(公告)日：1999-10-26
申请号：US736301
申请日：1996-10-24
申请人： Jeffrey Peter Gambino , Son Van Nguyen , Reinhard Stengl
发明人： Jeffrey Peter Gambino , Son Van Nguyen , Reinhard Stengl
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/02164 , H01L21/02129 , H01L21/022 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , Y10T428/24926
摘要： Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

64. 发明授权

US5855962A Flowable spin-on insulator 失效
标题翻译：可流动的自旋绝缘子
公开(公告)号：US5855962A
公开(公告)日：1999-01-05
申请号：US780373
申请日：1997-01-09
申请人： Donna Rizzone Cote , Son Van Nguyen
发明人： Donna Rizzone Cote , Son Van Nguyen
IPC分类号： B05D7/00 , B05D7/24 , C03C17/22 , C03C17/34 , C03C17/42 , C08G77/395 , C08G77/398 , C09D183/08 , C09D183/14 , H01L21/316 , B05D3/02
CPC分类号： C03C17/3435 , C03C17/225 , C03C17/3441 , C03C17/42 , C08G77/395 , C08G77/398 , C09D183/08 , C09D183/14 , H01L21/316 , C03C2217/281 , C03C2217/283 , C03C2217/285 , H01L21/31625 , Y10S438/918
摘要： A spin on insulating coating with ionic barrier properties is formed on a substrate, by mixing a P or B containing material such as phosphazene or borazine with a solution of silsesquioxane, spin coating on a substrate to form a film of pre-determined thickness. The coated film is cured in a step wise manner to drive out the solvents and most of the H and OH groups, with the resulting film having a composition SiONX, where X can be B, P, F and mixtures thereof. The amount of P, B or other elements are predetermined by calculating the solids in the silsesquioxane and adding suitable amount of borazine or phosphazene. The coated and cured film fills and planarizes any topography on the substrate created by etching trenches, forming gate stacks or metal lines. In one of the variation, the substrate has a layer of insulating material disposed thereon prior to the application of the spin-on insulator.
摘要翻译：在衬底上形成具有离子阻挡性能的绝缘涂层上的旋涂，通过将含有P或B的材料如磷腈或环硼氮烷与硅倍半氧烷溶液混合，在衬底上旋涂以形成预定厚度的膜。涂覆的膜以逐步方式固化以排出溶剂和大部分H和OH基团，所得膜具有组成SiONX，其中X可以是B，P，F及其混合物。 P，B或其它元素的量通过计算倍半硅氧烷中的固体并加入适量的环硼氮烷或磷腈预先确定。涂覆和固化的膜填充并平面化通过蚀刻沟槽，形成栅极堆叠或金属线产生的衬底上的任何形貌。在其中一个变型中，在施加旋涂绝缘体之前，衬底具有设置在其上的绝缘材料层。

65. 发明申请

US20100187502A1 ENCLOSED NANOTUBE STRUCTURE AND METHOD FOR FORMING 失效
标题翻译：封装的纳米结构和形成方法
公开(公告)号：US20100187502A1
公开(公告)日：2010-07-29
申请号：US11419329
申请日：2006-05-19
申请人： Jeffrey Peter Gambino , Son Van Nguyen
发明人： Jeffrey Peter Gambino , Son Van Nguyen
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： B82Y10/00 , G11C13/025 , H01L21/7682 , H01L29/0665 , H01L29/685 , H01L29/86 , H01L51/0048 , H01L51/0554 , H01L2221/1094
摘要： A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.
摘要翻译：一种半导体器件及相关的成型方法。半导体器件包括形成在第一导电构件上的导电纳米管，使得第一间隙存在于导电纳米管的底侧和第一导电构件的顶侧之间。在导电性纳米管上形成第二绝缘层。在导电纳米管的顶侧和第二绝缘层的第一部分之间存在第二间隙。第一通孔开口和第二通孔开口各自延伸穿过第二绝缘层并进入第二间隙。

66. 发明申请

US20080157270A1 Metal to Metal Low-K Antifuse 审中-公开
标题翻译：金属与金属Low-K防腐剂
公开(公告)号：US20080157270A1
公开(公告)日：2008-07-03
申请号：US11618757
申请日：2006-12-30
申请人： Deok-kee Kim , Anil K. Chinthakindi , Son Van Nguyen , Kelly Malone , Byeongju Park
发明人： Deok-kee Kim , Anil K. Chinthakindi , Son Van Nguyen , Kelly Malone , Byeongju Park
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage. In one embodiment herein the voltage can be supplemented by heating through application of voltage through the first conductor which helps change the resistance of the antifuse element region.
摘要翻译：本发明的实施例一般涉及熔丝和反熔丝结构，并且包括定位在基板内的铜导体和第一导体上的金属盖。低k电介质位于基板和金属盖上。电介质上的氮化钽电阻器，电阻器位于金属帽的上方，使得电介质的反熔丝元件区域位于电阻器和金属帽之间。电介质的反熔丝元件区域适于通过施加电阻器和铜导体/金属帽之间的电压差来改变电阻值。在施加电压之后，反熔丝元件区域具有第一高电阻（更紧密地匹配绝缘体）和施加电压之后的第二较低电阻（更接近地匹配导体）。在本文的一个实施例中，可以通过施加通过第一导体的电压进行加热来补充电压，这有助于改变反熔丝元件区域的电阻。

67. 发明申请

US20080132055A1 HARDMASK FOR IMPROVED RELIABILITY OF SILICON BASED DIELECTRICS 失效
标题翻译：用于改善基于硅的电介质的可靠性的HARDMASK
公开(公告)号：US20080132055A1
公开(公告)日：2008-06-05
申请号：US12016594
申请日：2008-01-18
申请人： Son Van Nguyen , Michael Lane , Stephen M. Gates , Xiao H. Liu , Vincent J. McGahay , Sanjay C. Mehta , Thomas M. Shaw
发明人： Son Van Nguyen , Michael Lane , Stephen M. Gates , Xiao H. Liu , Vincent J. McGahay , Sanjay C. Mehta , Thomas M. Shaw
IPC分类号： H01L21/4763
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/3122 , H01L21/76807 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10T428/24802 , H01L2924/00
摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.
摘要翻译：本发明提供了一种硬掩模，其位于具有嵌入其中的至少一个导电特征的低k电介质材料的表面上。硬掩模包括邻近低k电介质材料的气密氧化物材料的下部区域，以及包含位于密封氧化物材料上方的Si，C和H原子的上部区域。本发明还提供了制造本发明的硬掩模的方法以及形成包含该硬掩模的互连结构的方法。

68. 发明授权

US07117583B2 Method and apparatus using a pre-patterned seed layer for providing an aligned coil for an inductive head structure 失效
标题翻译：使用预图案种子层的方法和装置，用于提供用于感应头部结构的对准线圈
公开(公告)号：US07117583B2
公开(公告)日：2006-10-10
申请号：US10101196
申请日：2002-03-18
申请人： Thomas Edward Dinan , Jeffrey S. Lille , Son Van Nguyen , Hugo Alberto Emilio Santini
发明人： Thomas Edward Dinan , Jeffrey S. Lille , Son Van Nguyen , Hugo Alberto Emilio Santini
IPC分类号： G11B5/17 , C25D7/06
CPC分类号： G11B5/486 , G11B5/17 , G11B5/313 , G11B5/3163 , G11B5/3967 , H01F17/0006 , H01F41/043 , H01F41/046 , Y10T29/4902 , Y10T29/4906 , Y10T29/49062 , Y10T29/49064 , Y10T29/49073
摘要： A method and apparatus using a pre-patterned seed layer for providing an aligned coil for an inductive head structure. The method uses an aligned process where the base plate imprint is fabricated on an electrically insulating layer and the reversed image is fabricated and etched into the coil insulation material, e.g., hard bake photoresist to alleviate the problems associated with complete ion removal of the seed layer between high aspect ratio coils. The method would also not be prone to plating non-uniformities (voids), and would not be subject to seed layer undercutting in a wet etch step process.
摘要翻译：一种使用预先图案化种子层来提供用于感应头部结构的对准线圈的方法和装置。该方法使用对准的工艺，其中基板印版制造在电绝缘层上，并且反转的图像被制造并蚀刻到线圈绝缘材料中，例如硬烘烤光致抗蚀剂以减轻与种子层的完全离子去除相关的问题在高纵横比线圈之间。该方法也不易于电镀不均匀（空隙），并且在湿法蚀刻步骤中不会经受种子层底切。

69. 发明授权

US07075750B2 Apparatus for patterning a self-aligned coil using a damascene process 有权
标题翻译：用于使用镶嵌工艺图案化自对准线圈的装置
公开(公告)号：US07075750B2
公开(公告)日：2006-07-11
申请号：US10652877
申请日：2003-08-29
申请人： Daniel Wayne Bedell , Quang Le , Edward Hin Pong Lee , Son Van Nguyen , Vladimir Nikitin , Murali Ramasubramanian
发明人： Daniel Wayne Bedell , Quang Le , Edward Hin Pong Lee , Son Van Nguyen , Vladimir Nikitin , Murali Ramasubramanian
IPC分类号： G11B5/147
CPC分类号： G11B5/127
摘要： An apparatus for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.
摘要翻译：公开了一种使用镶嵌工艺图案化自对准线圈的装置。在设置在第一极层上的第一绝缘层中形成线圈腔。隔离层/籽晶层沿绝缘层中的线圈袋的壁被沉积。在线圈袋中形成铜，并在绝缘层上形成铜。铜平坦化到绝缘层。自对准线圈工艺将更多的铜包装到相同的线圈袋中，并松弛线圈对准公差。由于在写入期间线圈的间隔更加有效和均匀以减少头部的积聚，所以防止了突起。

70. 发明授权

US06664026B2 Method of manufacturing high aspect ratio photolithographic features 有权
公开(公告)号：US06664026B2
公开(公告)日：2003-12-16
申请号：US09815540
申请日：2001-03-22
申请人： Son Van Nguyen , Neil Leslie Robertson , Thomas Edward Dinan , Thao Duc Pham
发明人： Son Van Nguyen , Neil Leslie Robertson , Thomas Edward Dinan , Thao Duc Pham
IPC分类号： G03F700
CPC分类号： G03F7/094 , G03F7/40 , G11B5/17 , G11B5/3116 , G11B5/3163 , H01L21/0332 , H01L21/042
摘要： An etch barrier to be used in a photolithograph process is disclosed. A silicon rich etch barrier is deposited on a substrate using a low energy deposition technique. A diamond like carbon layer is deposited on the silicon rich etch barrier. Photoresist is then placed on this etch barrier DLC combination. To form photolithographic features, successive steps of oxygen and flourine reactive ion etching is used.

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