专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07534726B2 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US07534726B2
公开(公告)日：2009-05-19
申请号：US11682632
申请日：2007-03-06
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L21/311
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

62. 发明申请

US20060292795A1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US20060292795A1
公开(公告)日：2006-12-28
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

63. 发明申请

US20100096681A1 Cell structure for a semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件的单元结构及其制造方法
公开(公告)号：US20100096681A1
公开(公告)日：2010-04-22
申请号：US12654255
申请日：2009-12-15
申请人： Kyoung-Yun Baek , Yong-Sun Ko , Hak Kim , Yong-Kug Bae
发明人： Kyoung-Yun Baek , Yong-Sun Ko , Hak Kim , Yong-Kug Bae
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10888
摘要： In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.
摘要翻译：在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。位线可以与第三区域的位线接触焊盘连接。尽管6F2结构的单元电池，电池结构也可以更容易地形成。多个有源区域可以具有包括主轴和短轴的椭圆形状。多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心相邻活动行中的区域。

64. 发明申请

US20090090899A1 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090090899A1
公开(公告)日：2009-04-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

65. 发明授权

US07498253B2 Local interconnection method and structure for use in semiconductor device 失效
标题翻译：用于半导体器件的局部互连方法和结构
公开(公告)号：US07498253B2
公开(公告)日：2009-03-03
申请号：US11679722
申请日：2007-02-27
申请人： Sung-Un Kwon , Yong-Sun Ko
发明人： Sung-Un Kwon , Yong-Sun Ko
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76808 , H01L21/76895
摘要： A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.
摘要翻译：用于形成其的局部互连配线结构方法通过形成公共孔径来减小栅电极的局部互连层与有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径半导体衬底的绝缘膜。形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。然后去除第二蚀刻掩模图案。然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

66. 发明授权

US07091117B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07091117B2
公开(公告)日：2006-08-15
申请号：US10836694
申请日：2004-04-30
申请人： Jae-Woo Kim , Yong-Sun Ko , Sang-Sup Jeong
发明人： Jae-Woo Kim , Yong-Sun Ko , Sang-Sup Jeong
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66553 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823437 , H01L27/10873
摘要： A method of fabricating a semiconductor device including sequentially forming a polysilicon layer, a first insulating layer, and a photoresist layer over a gate oxide film positioned on a semiconductor substrate. A photoresist pattern with a first groove is formed by selectively patterning the photoresist layer to partially expose a surface of the first insulating layer. A second insulating layer is formed over the photoresist pattern with the first groove and over the exposed surface of the first insulating layer. A sacrificial spacer is formed on each inner wall of the first groove by etching back the second insulating layer and forming a second groove in the first insulating layer in communication with the first groove to expose a surface of the polysilicon layer at the bottom of the second groove. The photoresist pattern is removed, and an arbitrary layer pattern is formed over the polysilicon layer at the bottom of the second groove. The sacrificial spacers and first insulating layer are removed, and a gate electrode is formed by etching the polysilicon layer using the arbitrary layer pattern as a mask.
摘要翻译：一种制造半导体器件的方法，包括在位于半导体衬底上的栅极氧化膜上顺序地形成多晶硅层，第一绝缘层和光致抗蚀剂层。通过选择性地图案化光致抗蚀剂层以部分地暴露第一绝缘层的表面来形成具有第一凹槽的光刻胶图案。在光致抗蚀剂图案上形成有第一绝缘层和第一绝缘层的暴露表面上的第一绝缘层。通过蚀刻第二绝缘层并在与第一凹槽连通的第一绝缘层中形成第二凹槽，在第二凹槽的每个内壁上形成牺牲隔离物，以暴露第二凹槽底部的多晶硅层的表面槽。去除光致抗蚀剂图案，并且在第二凹槽底部的多晶硅层上形成任意层图案。去除牺牲间隔物和第一绝缘层，并且通过使用任意层图案作为掩模蚀刻多晶硅层来形成栅电极。

67. 发明授权

US06838330B2 Method of forming a contact hole of a semiconductor device 有权
标题翻译：形成半导体器件的接触孔的方法
公开(公告)号：US06838330B2
公开(公告)日：2005-01-04
申请号：US10445843
申请日：2003-05-28
申请人： Bong-Ho Moon , Ju-Yun Cheol , Yong-Sun Ko , In-Seak Hwang
发明人： Bong-Ho Moon , Ju-Yun Cheol , Yong-Sun Ko , In-Seak Hwang
IPC分类号： H01L21/768 , H01L21/60 , H01L21/8238
CPC分类号： H01L21/02063 , H01L21/76897
摘要： A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).
摘要翻译：形成能够防止层间电介质图案的过度蚀刻的半导体器件的接触孔的方法包括形成包括第一绝缘层图案，导电层图案，封盖绝缘层图案和第二绝缘体的栅极图案层图案; 在所述栅极图案的侧壁上使用绝缘材料形成间隔物; 在其上形成有栅极图案和间隔物的基板上形成层间电介质; 形成用于通过蚀刻所述层间电介质来暴露所述衬底的接触孔和层间电介质图案; 在间隔物的侧壁和层间介质图案上形成衬垫; 并使用清洁溶液清洗所得到的结构。清洗液最好包括臭氧水和氟化氢（HF）。

68. 发明授权

US07667221B2 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07667221B2
公开(公告)日：2010-02-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

69. 发明授权

US07534704B2 Thin layer structure and method of forming the same 失效
标题翻译：薄层结构及其形成方法
公开(公告)号：US07534704B2
公开(公告)日：2009-05-19
申请号：US11449839
申请日：2006-06-09
申请人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
发明人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02667 , H01L21/76262 , H01L27/1203
摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.
摘要翻译：在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。在第一开口中形成包括单晶硅的一种或多种初步种子图案。在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。第二绝缘图案包括具有平坦底部的第二开口。在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

70. 发明授权

US07452773B2 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US07452773B2
公开(公告)日：2008-11-18
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式