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61. 发明申请

US20120068174A1 ELECTRICAL MASK INSPECTION 失效
标题翻译：电磁屏蔽检查
公开(公告)号：US20120068174A1
公开(公告)日：2012-03-22
申请号：US12886612
申请日：2010-09-21
申请人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
IPC分类号： H01L23/522 , H01L21/66 , H01L21/768
CPC分类号： H01L23/544 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
摘要翻译：公开了一种用于电气掩模检查的装置和方法。在两个金属层和通孔层之间形成扫描链。三层之一是被测功能层，另外两层是测试层。使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

62. 发明申请

US20110163383A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20110163383A1
公开(公告)日：2011-07-07
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

63. 发明申请

US20100330763A1 METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS 有权
标题翻译：创建不对称场效应晶体管的方法
公开(公告)号：US20100330763A1
公开(公告)日：2010-12-30
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对与基底垂直。

64. 发明授权

US07804140B2 Field effect transistor with reduced shallow trench isolation induced leakage current 失效
标题翻译：场效应晶体管减少浅沟槽隔离引起的漏电流
公开(公告)号：US07804140B2
公开(公告)日：2010-09-28
申请号：US12041967
申请日：2008-03-04
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译：沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。

65. 发明授权

US07732270B2 Device having enhanced stress state and related methods 有权
标题翻译：具有增强的应力状态和相关方法的装置
公开(公告)号：US07732270B2
公开(公告)日：2010-06-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

66. 发明授权

US07709910B2 Semiconductor structure for low parasitic gate capacitance 有权
标题翻译：用于低寄生栅极电容的半导体结构
公开(公告)号：US07709910B2
公开(公告)日：2010-05-04
申请号：US11738666
申请日：2007-04-23
申请人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
发明人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/76814 , H01L21/7682 , H01L21/76832 , H01L21/76844 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
摘要翻译：半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平。由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

67. 发明申请

US20090178012A1 METHODOLOGY FOR IMPROVING DEVICE PERFORMANCE PREDICTION FROM EFFECTS OF ACTIVE AREA CORNER ROUNDING 失效
标题翻译：改善活动区域拐角影响装置性能预测的方法
公开(公告)号：US20090178012A1
公开(公告)日：2009-07-09
申请号：US11971015
申请日：2008-01-08
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.
摘要翻译：一种用于建模半导体晶体管器件结构的系统和方法，所述半导体晶体管器件结构具有设计长度的导线特征，所述导线特征与待建模的电路中的晶体管器件的栅极连接，所述晶体管包括有源器件（RX）形成并且其上延伸有导线特征。该方法包括提供分析模型表示，其包括用于建模影响有源器件区域宽度的光刻火炬效应的功能; 并且从建模功能将有源器件区域宽度（deltaW加法器）的有效变化与距离RX区域的限定边缘的距离的函数相关联。然后，器件的晶体管紧凑型模型中的晶体管模型参数值被更新为包括要添加到内置deltaW值的ΔW加法器值。在模拟中使用的网表包括deltaW加法器值，以更精确地描述被建模的晶体管器件的特性，包括对晶体管器件参数的光刻拐角舍入效应的建模。

68. 发明申请

US20090072312A1 Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS 审中-公开
标题翻译：金属高K（MHK）双栅应力工程使用混合方向（HOT）CMOS
公开(公告)号：US20090072312A1
公开(公告)日：2009-03-19
申请号：US11855204
申请日：2007-09-14
申请人： Leland Chang , Shreesh Narasimha , Vijay Narayanan , Jeffrey W. Sleight
发明人： Leland Chang , Shreesh Narasimha , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/665 , H01L29/66545
摘要： A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack.
摘要翻译：混合取向技术（HOT）CMOS结构由拉伸应力NFET栅极堆叠和压缩应力PFET栅极堆叠构成，其中每个栅极堆叠由高介电常数氧化物/金属组成，并且其中源拉伸应力NFET栅极堆叠和压应力PFET栅极堆叠是高k金属栅极堆叠中的金属。

69. 发明授权

US07329923B2 High-performance CMOS devices on hybrid crystal oriented substrates 失效
标题翻译：混合晶体取向基板上的高性能CMOS器件
公开(公告)号：US07329923B2
公开(公告)日：2008-02-12
申请号：US10250241
申请日：2003-06-17
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L27/01
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

70. 发明授权

US07274072B2 Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance 有权
标题翻译：用于改善电池稳定性和性能的混合体SOI-6T-SRAM电池
公开(公告)号：US07274072B2
公开(公告)日：2007-09-25
申请号：US11108012
申请日：2005-04-15
申请人： Leland Chang , Shreesh Narasimha , Norman J. Rohrer , Jeffrey W. Sleight
发明人： Leland Chang , Shreesh Narasimha , Norman J. Rohrer , Jeffrey W. Sleight
IPC分类号： H01L29/72
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译：本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

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