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61. 发明授权

US5930500A Parallel processor implementation of net routing 失效
标题翻译：并行处理器实现网络路由
公开(公告)号：US5930500A
公开(公告)日：1999-07-27
申请号：US798880
申请日：1997-02-11
申请人： Ranko Scepanovic , Edwin Jones , Alexander E. Andreev
发明人： Ranko Scepanovic , Edwin Jones , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.
摘要翻译：公开了一种使多个处理器并联处理的有效性最大化的方法来连接集成电路网的引脚。该方法需要将引脚分成一组引脚，并且该引脚组进一步划分成该组引脚的元组。使用最小生成树算法连接集合和元集，并且使连接的集合共享引脚，从而确保整个网络互连而不在路由中创建环路。另外，由于分区和分区的平均数大致相同，所以处理器之间可以容易地平衡工作负载。

62. 发明授权

US5914888A Advanced modular cell placement system with coarse overflow remover 失效
标题翻译：先进的模块化电池放置系统，具有粗糙的溢流去除器
公开(公告)号：US5914888A
公开(公告)日：1999-06-22
申请号：US672334
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method for optimizing cell placement for integrated circuit design is provided herein. The method comprises the steps of segmenting an integrated circuit surface abstraction into a plurality of regions; assigning a plurality of cells to one of the regions; creating a list of said plurality of cells in order of decreasing cell height; reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region; and thereafter assigning the remaining cells outside of the region.
摘要翻译：本文提供了一种用于优化集成电路设计的单元布局的计算机实现方法。该方法包括将集成电路表面抽象分割成多个区域的步骤; 将多个单元分配给所述区域之一; 按照降低单元高度的顺序创建所述多个单元的列表; 根据列表的顺序重新分配所述单元，使得将单元分配给所述区域，直到不足以将单元再次配合到该区域中的能力为止; 然后将剩余的单元格分配给该区域外。

63. 发明授权

US5889329A Tri-directional interconnect architecture for SRAM 失效
标题翻译：用于SRAM的三向互连架构
公开(公告)号：US5889329A
公开(公告)日：1999-03-30
申请号：US517339
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L23/535
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

64. 发明授权

US5870312A Advanced modular cell placement system with dispersion-driven levelizing system 失效
标题翻译：具有色散驱动调平系统的高级模块化放置系统
公开(公告)号：US5870312A
公开(公告)日：1999-02-09
申请号：US672652
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimizing the density of cells located on a surface of a semiconductor chip divided into a plurality of rectangular regions is provided herein. The corners of these regions define nodes. The system comprises computing an average local cell density for regions adjacent to each node and deforming these regions by relocating nodes to positions that minimize a cost function associated with the densities of the new deformed regions bordering the relocated nodes.
摘要翻译：本发明提供一种用于优化位于分成多个矩形区域的半导体芯片的表面上的单元的密度的系统。这些区域的角落定义了节点。该系统包括计算与每个节点相邻的区域的平均局部小区密度，并通过将节点重新定位到最小化与重定位节点邻接的新变形区域的密度相关联的成本函数的位置来变形这些区域。

65. 发明授权

US5864165A Triangular semiconductor NAND gate 失效
标题翻译：三角半导体NAND门
公开(公告)号：US5864165A
公开(公告)日：1999-01-26
申请号：US517451
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/772
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

66. 发明授权

US5796625A Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization 失效
标题翻译：物理设计自动化系统和使用模拟退火设计集成电路芯片的过程用“棋盘和摆动”优化
公开(公告)号：US5796625A
公开(公告)日：1998-08-18
申请号：US609359
申请日：1996-03-01
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes. An initial temperature for the actual simulated annealing operation is determined by performing simulated annealing without cell swaps with different temperature, and selecting the temperature at which a cost function such as total wirelength does not significantly change.
摘要翻译：集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。对每个抖动的每个颜色依次执行模拟退火。在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。在每个操作结束时，更新芯片的副本。棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。这些区域可以具有矩形，三角形或六边形形状。实际模拟退火操作的初始温度是通过进行模拟退火而不使用不同温度的电池互换来确定的，并且选择诸如总线长度的成本函数不会显着改变的温度。

67. 发明授权

US5784287A Physical design automation system and process for designing integrated circuit chips using generalized assignment 失效
标题翻译：物理设计自动化系统和使用广义分配设计集成电路芯片的过程
公开(公告)号：US5784287A
公开(公告)日：1998-07-21
申请号：US536004
申请日：1995-09-29
申请人： Ranko Scepanovic , James S. Koford , Edwin R. Jones , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Ranko Scepanovic , James S. Koford , Edwin R. Jones , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A process for designing an integrated circuit chip s comprises specifying a plurality of regions on the chip in which a plurality of objects are to be placed, such that there are more of the objects than the regions, and specifying penalties for the objects to be placed in the regions respectively. The objects can be microelectronic cells, interconnect wiring segments, etc. An assignment of the objects to the regions is constructed, and a number of objects for movement between the regions is selected. An optimal permutation of movement of the selected number of objects between the regions is computed such that a cost corresponding to the total penalties for the assignment is maximally reduced, and the assignment is modified by moving the selected number of objects through the optimal permutation. The process steps are repeated iteratively such that a maximum number of objects which will produce a maximal reduction in cost is moved during each iteration. The optimal permutation is determined by computing penalty changes for moving the objects between the regions respectively, defining a penalty change scale having a plurality of subintervals, assigning the objects to the penalty change scale in accordance with their penalty changes, and moving the objects which have penalty changes in a number of subintervals having largest values of negative penalty change.
摘要翻译：设计集成电路芯片的过程包括在芯片上指定多个对象要放置的多个区域，使得存在比区域更多的对象，并且指定要放置的对象的处罚分别在区域。物体可以是微电子单元，互连布线段等。构造对象到区域的分配，并且选择用于在区域之间移动的多个对象。计算在区域之间所选择的对象数量的移动的最佳排列，使得对应于分配的总惩罚的成本被最大程度地减少，并且通过移动所选择的对象数量通过最优排列来修改分配。迭代地重复处理步骤，使得在每次迭代期间移动将产生最大成本降低的最大数量的对象。通过计算用于在区域之间移动对象的惩罚变化来确定最优排列，定义具有多个子区间的惩罚改变量表，根据其惩罚改变将对象分配给惩罚改变量表，以及移动具有在具有最大值的负惩罚变化的多个子区间中的惩罚变化。

68. 发明授权

US07472358B2 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US07472358B2
公开(公告)日：2008-12-30
申请号：US11260517
申请日：2005-10-27
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

69. 发明授权

US07328423B2 Method for evaluating logic functions by logic circuits having optimized number of and/or switches 失效
标题翻译：用于通过具有优化的数量和/或开关的逻辑电路来评估逻辑功能的方法
公开(公告)号：US07328423B2
公开(公告)日：2008-02-05
申请号：US11055752
申请日：2005-02-10
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.
摘要翻译：一种用于创建具有优化数量的AND / OR开关的逻辑电路的方法，其评估在高级描述中定义的逻辑功能。通过分析用于定义逻辑功能的运算符之间的依赖关系，本发明可以简化用于定义逻辑功能的高级描述中使用的功能步骤，从而创建具有优化数量的AND / OR开关的逻辑电路。

70. 发明授权

US07315993B2 Verification of RRAM tiling netlist 失效
标题翻译：验证RRAM平铺网表
公开(公告)号：US07315993B2
公开(公告)日：2008-01-01
申请号：US10999468
申请日：2004-11-30
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F9/45 , G06F17/50 , G06F11/00 , G11C29/00
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译：本发明提供了一种RRAM拼接网表的验证方法。该方法可以包括以下步骤。属性RRAM平铺网表的所有网络和单元格的“memory_number”，“clock_number”和“netlist_part”被设置为0.值为0的布尔值分配给RRAM平铺网表的所有地网，布尔值1 被分配给RRAM平铺网表的所有电网。对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。。。，N.

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