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1. 发明授权

US07404166B2 Method and system for mapping netlist of integrated circuit to design 失效
标题翻译：将集成电路网表映射到设计的方法和系统
公开(公告)号：US07404166B2
公开(公告)日：2008-07-22
申请号：US11257289
申请日：2005-10-24
申请人： Alexander E. Andreev , Pavel Panteleev , Andrey A. Nikitin
发明人： Alexander E. Andreev , Pavel Panteleev , Andrey A. Nikitin
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/64
摘要： The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
摘要翻译：本发明提供了一种用于将集成电路的网表映射到设计的方法。该方法包括以下步骤。混沌算法用于从网表中为单元格设计获得最有利的位置。 Kuhn算法用于将网表中的每个单元格分配给模板中的单元，使得对于网表的每个单元，其在模板中的位置尽可能靠近其通过混沌算法获得的位置。应用模拟退火优化技术减少设计线长度的总和。

2. 发明授权

US07103868B2 Optimizing depths of circuits for Boolean functions 有权
标题翻译：优化布尔函数的电路深度
公开(公告)号：US07103868B2
公开(公告)日：2006-09-05
申请号：US10291982
申请日：2002-11-12
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Boolean circuits are designed with minimal depth by calculating the depth of an existing circuit. Those subtrees having a non-regular root cell (i.e., cells having other than one child or having a child of a type different from the cell) are balanced by constructing a new subtree. The cells are then iteratively transformed with parent and/or grandparent cells to reduce the depth of the circuit. The transformation may include balancing the subtree to make the parent cell the same type as the selected cell, or by creating a new cell as parent to the selected cell.
摘要翻译：通过计算现有电路的深度，布尔电路设计的最小深度。具有非正规根细胞（即，具有不同于一个子代的细胞或具有不同于细胞的子类的细胞）的子树通过构建新的子树来平衡。然后用母体和/或祖母细胞迭代转化细胞以减少电路的深度。转换可以包括平衡子树以使父单元与所选择的单元相同，或通过将新单元创建为所选单元格的父单元。

3. 发明授权

US07111264B2 Process and apparatus for fast assignment of objects to a rectangle 有权
标题翻译：将对象快速分配给矩形的过程和设备
公开(公告)号：US07111264B2
公开(公告)日：2006-09-19
申请号：US10688460
申请日：2003-10-17
申请人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
发明人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译：通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别。

4. 发明授权

US07822099B2 Digital Gaussian noise simulator 有权
标题翻译：数字高斯噪声模拟器
公开(公告)号：US07822099B2
公开(公告)日：2010-10-26
申请号：US11758975
申请日：2007-06-06
申请人： Andrey A. Nikitin , Alexander E. Andreev , Igor A. Vikhliantsev
发明人： Andrey A. Nikitin , Alexander E. Andreev , Igor A. Vikhliantsev
IPC分类号： H04B1/69 , G06F1/02 , G06F7/58 , H03K3/84
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j ⁢ ⁢ or ⁢ ⁢ s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
摘要翻译：高斯噪声由离散模拟ri，j模拟。选择第一参数α和多个第一和第二整数i和j。识别多个点i，j，并且基于α，i和j针对每个点计算幅度si，j。离散的模拟ri，j基于相应的si，j。给出α= 2 B-A 2 B和D> i≥0和2C>j≥0的实例，其中B≥0,2B> A> 0，C≥1和D≥1，并且幅度si，j = 1-αi +αi·1-α2 C·j·肯·杜·斯D-1，j = 1-αD-1 +αD·1·1 2 C·j。在一些实施例中，基于α和i定义段。根据j的相应值将该段划分成点，并且对该段的每个点计算大小。对于i的每个值迭代地重复定义和分割段并计算幅度。

5. 发明授权

US07472358B2 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US07472358B2
公开(公告)日：2008-12-30
申请号：US11260517
申请日：2005-10-27
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

6. 发明授权

US07328423B2 Method for evaluating logic functions by logic circuits having optimized number of and/or switches 失效
标题翻译：用于通过具有优化的数量和/或开关的逻辑电路来评估逻辑功能的方法
公开(公告)号：US07328423B2
公开(公告)日：2008-02-05
申请号：US11055752
申请日：2005-02-10
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.
摘要翻译：一种用于创建具有优化数量的AND / OR开关的逻辑电路的方法，其评估在高级描述中定义的逻辑功能。通过分析用于定义逻辑功能的运算符之间的依赖关系，本发明可以简化用于定义逻辑功能的高级描述中使用的功能步骤，从而创建具有优化数量的AND / OR开关的逻辑电路。

7. 发明授权

US07315993B2 Verification of RRAM tiling netlist 失效
标题翻译：验证RRAM平铺网表
公开(公告)号：US07315993B2
公开(公告)日：2008-01-01
申请号：US10999468
申请日：2004-11-30
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F9/45 , G06F17/50 , G06F11/00 , G11C29/00
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译：本发明提供了一种RRAM拼接网表的验证方法。该方法可以包括以下步骤。属性RRAM平铺网表的所有网络和单元格的“memory_number”，“clock_number”和“netlist_part”被设置为0.值为0的布尔值分配给RRAM平铺网表的所有地网，布尔值1 被分配给RRAM平铺网表的所有电网。对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。。。，N.

8. 发明授权

US07257807B2 Method for optimizing execution time of parallel processor programs 失效
标题翻译：优化并行处理器程序执行时间的方法
公开(公告)号：US07257807B2
公开(公告)日：2007-08-14
申请号：US10667812
申请日：2003-09-22
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F8/443 , G06F8/314 , G06F8/51
摘要： The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses. Moreover, when the processor integrated circuit executes a parallel processor command, the processor integrated circuit executes all subcommands included in the parallel processor command in parallel in one clock cycle.
摘要翻译：本发明涉及并行处理器语言，用于将C ++程序转换为并行处理器语言的方法以及用于优化并行处理器程序的执行时间的方法。在本发明的示例性方面，用于定义处理器集成电路的并行处理器程序包括具有地址的多个处理器命令。多个处理器命令可以包括起始处理器命令，并且多个处理器命令中的每一个包括一个或多个子命令。当处理器集成电路执行并行处理器程序时，处理器集成电路首先执行起始处理器命令，然后基于地址的顺序执行多个处理器命令中的其余部分。此外，当处理器集成电路执行并行处理器命令时，处理器集成电路在一个时钟周期内并行地执行并行处理器命令中包括的所有子命令。

9. 发明授权

US07210113B2 Process and apparatus for placing cells in an IC floorplan 有权
标题翻译：将电池放置在IC平面图中的工艺和设备
公开(公告)号：US07210113B2
公开(公告)日：2007-04-24
申请号：US10830542
申请日：2004-04-23
申请人： Alexander E. Andreev , Andrey A. Nikitin , Igor A. Vikhliantsev
发明人： Alexander E. Andreev , Andrey A. Nikitin , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. The coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.
摘要翻译：通过在模块中创建单元格群，将单元格放置在集成电路平面布置图中，每个簇由连接到模块中的至少一个触发器的路径中的单元或者不连接到任何翻转的路径的单元组成 -flop。区域在布局图中定义，用于放置模块，并将集群放置在模块中的最佳位置，并将模块放置在区域中的最佳位置。有选择地重新计算电线，模块和集群的坐标。群集在平面图中移动以获得更均匀的密度，并且将模块分配给基于模块坐标的区域。

10. 发明授权

US07082593B2 Method and apparatus of IC implementation based on C++ language description 失效
标题翻译：基于C ++语言描述的IC实现方法和装置
公开(公告)号：US07082593B2
公开(公告)日：2006-07-25
申请号：US10621737
申请日：2003-07-17
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.
摘要翻译：本发明涉及基于C ++语言描述的IC实现的方法和装置。在本发明的一个示例性方面，用于通过IC评估C ++描述的方法包括以下步骤。首先，提供包括C ++程序的C ++描述。然后，C ++程序被存储在IC的第一存储器模块（例如，ROM等中）中。接下来，可以向IC提供标量输入和/或输入阵列。然后，C ++程序可以由IC的控制装置模块执行。接下来，可以从IC读取标量输出和/或输出阵列。

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