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61. 发明申请

US20070152273A1 High performance circuit with metal and polygate electrodes 有权
标题翻译：具有金属和多孔电极的高性能电路
公开(公告)号：US20070152273A1
公开(公告)日：2007-07-05
申请号：US11323564
申请日：2005-12-30
申请人： Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Young-Hee Kim , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen , Ying Zhang
发明人： Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Young-Hee Kim , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen , Ying Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/823857 , H01L21/28044 , H01L21/28088 , H01L21/823842 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.
摘要翻译：一种半导体结构及其制造方法，其中该结构包括至少一个nFET器件和至少一个pFET器件，其中至少一个器件是薄化的含Si门控器件，另一个器件是金属门控器件被提供。也就是说，提供半导体结构，其中nFET或pFET器件中的至少一个包括包括稀薄的含Si电极，即多晶硅电极和上覆的第一金属的栅极电极堆叠，而另一个器件包括栅电极堆叠，其至少包括第一金属栅极，而没有变薄的含Si电极。

62. 发明授权

US07108797B2 Method of fabricating a shiftable magnetic shift register 有权
标题翻译：制造可移动磁移位寄存器的方法
公开(公告)号：US07108797B2
公开(公告)日：2006-09-19
申请号：US10787738
申请日：2004-02-25
申请人： Tze-chiang Chen , Stuart S. P. Parkin
发明人： Tze-chiang Chen , Stuart S. P. Parkin
IPC分类号： G11B5/127 , B44C1/22 , H01L21/00
CPC分类号： G11C11/14 , G11C19/02 , G11C19/0808 , G11C19/0841 , H01F10/14 , H01F10/265 , H01F41/26 , Y10T29/49021 , Y10T29/49043 , Y10T29/49052
摘要： A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.
摘要翻译：用于磁移位寄存器存储器系统的磁数据磁道可以通过形成交替的电介质层和/或硅层的多层叠层来制造。在该多层交替层中蚀刻约10微米高的具有100nm×100nm量级的横截面的通孔。通孔可能被蚀刻形成平滑或缺口的墙壁。通孔由交替类型的铁磁或亚铁磁性金属的电镀层填充。交替的铁磁或亚铁磁层由具有不同磁化或磁交换或磁各向异性的磁性材料组成。这些不同的磁特性允许磁畴壁在这些层之间的边界处的钉扎。或者，通孔用均匀的铁磁材料填充。磁畴壁由铁氧体或铁磁材料中的不连续部分形成，这些不规则发生在沿着通孔壁的凹口或凸起处。

63. 发明授权

US06914320B2 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof 有权
标题翻译：双层HDP CVD / PE CVD帽在先进的BEOL互连结构及其方法
公开(公告)号：US06914320B2
公开(公告)日：2005-07-05
申请号：US10807029
申请日：2004-03-23
申请人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
发明人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积通过等离子体增强化学气相沉积（PE CVD）工艺。还公开了一种用于形成BEOL金属化结构的方法。本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

64. 发明申请

US20050093100A1 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US20050093100A1
公开(公告)日：2005-05-05
申请号：US10700085
申请日：2003-11-03
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/762 , H01L27/12 , H01L27/144 , H01L31/0232 , H01L31/028 , H01L31/0352 , H01L31/105 , H01L31/18 , H01L31/117
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

65. 发明授权

US06885080B2 Deep trench isolation of embedded DRAM for improved latch-up immunity 有权
标题翻译：嵌入式DRAM的深沟槽隔离以提高闭锁电抗
公开(公告)号：US06885080B2
公开(公告)日：2005-04-26
申请号：US10082648
申请日：2002-02-22
申请人： Tze-Chiang Chen , Liang-Kai Han
发明人： Tze-Chiang Chen , Liang-Kai Han
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/092 , H01L27/108 , H01L29/00
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/76232 , H01L27/10829 , H01L27/10897
摘要： A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
摘要翻译：公开了一种用于阻止在半导体器件中产生的缺陷传播的保护结构。在示例性实施例中，该结构包括在半导体器件的存储器存储区域和半导体器件的逻辑电路区域之间形成的深沟槽隔离，深沟槽隔离件填充有绝缘材料。深沟槽隔离从而防止在逻辑电路区域中产生的晶体缺陷的传播不会传播到存储器存储区域中。

66. 发明授权

US06878611B2 Patterned strained silicon for high performance circuits 失效
标题翻译：用于高性能电路的图形应变硅
公开(公告)号：US06878611B2
公开(公告)日：2005-04-12
申请号：US10336147
申请日：2003-01-02
申请人： Devendra K. Sadana , Stephen W. Bedell , Tze-Chiang Chen , Kwang Su Choe , Keith E. Fogel
发明人： Devendra K. Sadana , Stephen W. Bedell , Tze-Chiang Chen , Kwang Su Choe , Keith E. Fogel
IPC分类号： H01L21/76 , H01L21/02 , H01L21/20 , H01L21/324 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L21/36
CPC分类号： H01L21/324 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02694 , H01L21/823807 , Y10S438/96
摘要： In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.
摘要翻译：在本发明的优选实施例中，描述了通过SiGe / SOI热混合工艺将图案化SOI区域转换为图案化SGOI（氧化硅上的硅 - 锗）的方法，以进一步增强嵌入式DRAM中逻辑电路的性能。 SGOI区域用作随后的Si生长的模板，使得Si被应变，并且Si中的电子和空穴具有较高的迁移率。

67. 发明授权

US06271578B1 Crack stops 有权
标题翻译：裂缝停止
公开(公告)号：US06271578B1
公开(公告)日：2001-08-07
申请号：US09218882
申请日：1998-12-22
申请人： Alexander R. Mitwalsky , Tze-Chiang Chen
发明人： Alexander R. Mitwalsky , Tze-Chiang Chen
IPC分类号： H01L29544
CPC分类号： H01L21/78
摘要： Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.
摘要翻译：描述了用于基本上防止沿着切割通道产生的裂纹的裂纹停止扩散到IC的有源区域。通过在芯片边缘附近的切割通道中的介电层的厚度产生不连续性来形成裂纹停止。不连续性可导致电介质层的厚度增加和/或减小。

68. 发明授权

US5185276A Method for improving low temperature current gain of bipolar transistors 失效
标题翻译：改善双极晶体管低温电流增益的方法
公开(公告)号：US5185276A
公开(公告)日：1993-02-09
申请号：US689673
申请日：1991-04-23
申请人： Tze-Chiang Chen , John D. Cressler
发明人： Tze-Chiang Chen , John D. Cressler
IPC分类号： H01L21/331 , H01L29/167 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/167 , H01L29/732 , G09G2300/023 , G09G2320/0276 , Y10S148/002 , Y10S148/01 , Y10S438/918 , Y10S438/919
摘要： A method for improving the low temperature current gain of silicon bipolar transistors by implanting a first and a second impurity of the same conductivity type into the base region to provide a high doping level base that increases bandgap narrowing without decreasing freeze-out activation energy. The second impurity is selected to have a higher ionization energy that that of the first impurity. The second impurity thereby freezes out sooner than the first impurity resulting in the freeze-out activation energy being equal to or greater than the energy with only the first impurity.
摘要翻译：一种用于通过将相同导电类型的第一和第二杂质注入基极区域来提高硅双极晶体管的低温电流增益的方法，以提供高掺杂水平的基极，其增加带隙变窄而不降低冷冻激活能。选择第二杂质具有比第一杂质更高的电离能。因此，第二杂质比第一杂质更早地冻结，导致冻结活化能等于或大于仅具有第一杂质的能量。

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