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1. 发明申请

US20070152273A1 High performance circuit with metal and polygate electrodes 有权
标题翻译：具有金属和多孔电极的高性能电路
公开(公告)号：US20070152273A1
公开(公告)日：2007-07-05
申请号：US11323564
申请日：2005-12-30
申请人： Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Young-Hee Kim , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen , Ying Zhang
发明人： Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Young-Hee Kim , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen , Ying Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/823857 , H01L21/28044 , H01L21/28088 , H01L21/823842 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.
摘要翻译：一种半导体结构及其制造方法，其中该结构包括至少一个nFET器件和至少一个pFET器件，其中至少一个器件是薄化的含Si门控器件，另一个器件是金属门控器件被提供。也就是说，提供半导体结构，其中nFET或pFET器件中的至少一个包括包括稀薄的含Si电极，即多晶硅电极和上覆的第一金属的栅极电极堆叠，而另一个器件包括栅电极堆叠，其至少包括第一金属栅极，而没有变薄的含Si电极。

2. 发明申请

US20070152276A1 High performance CMOS circuits, and methods for fabricating the same 审中-公开
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US20070152276A1
公开(公告)日：2007-07-05
申请号：US11323578
申请日：2005-12-30
申请人： John Arnold , Glenn Biery , Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Michael Gribelyuk , Young-Hee Kim , Barry Linder , Vijay Narayanan , Joseph Newbury , Vamsi Paruchuri , Michelle Steen
发明人： John Arnold , Glenn Biery , Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Michael Gribelyuk , Young-Hee Kim , Barry Linder , Vijay Narayanan , Joseph Newbury , Vamsi Paruchuri , Michelle Steen
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

3. 发明申请

US20070138563A1 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US20070138563A1
公开(公告)日：2007-06-21
申请号：US11303715
申请日：2005-12-16
申请人： Alessandro Callegari , Michael Chudzik , Bruce Doris , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen
发明人： Alessandro Callegari , Michael Chudzik , Bruce Doris , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

4. 发明申请

US20060237796A1 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
标题翻译：使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极
公开(公告)号：US20060237796A1
公开(公告)日：2006-10-26
申请号：US11111592
申请日：2005-04-21
申请人： Eduard Cartier , Matthew Copel , Bruce Doris , Rajarao Jammy , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri , Keith Wong
发明人： Eduard Cartier , Matthew Copel , Bruce Doris , Rajarao Jammy , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri , Keith Wong
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a worfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，至少一个nMOS器件包括栅堆叠，其包括栅极电介质，功能小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

5. 发明申请

US20070148838A1 Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
标题翻译：具有至少一个栅极金属和双栅极电介质的金属栅极CMOS
公开(公告)号：US20070148838A1
公开(公告)日：2007-06-28
申请号：US11320330
申请日：2005-12-28
申请人： Bruce Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri
发明人： Bruce Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

6. 发明申请

US20070173008A1 Introduction of metal impurity to change workfunction of conductive electrodes 有权
标题翻译：引入金属杂质来改变导电电极的功能
公开(公告)号：US20070173008A1
公开(公告)日：2007-07-26
申请号：US11336727
申请日：2006-01-20
申请人： Michael Chudzik , Bruce Doris , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Yun Wang , Keith Wong
发明人： Michael Chudzik , Bruce Doris , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Yun Wang , Keith Wong
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.
摘要翻译：提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数材料层与导电电极一起存在于电极堆叠中。金属杂质的选择取决于电极是否具有n型功函数或p型功函数。本发明还提供一种制造这种半导体结构的方法。金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

7. 发明申请

US20050048752A1 Ultra thin channel MOSFET 有权
标题翻译：超薄通道MOSFET
公开(公告)号：US20050048752A1
公开(公告)日：2005-03-03
申请号：US10650229
申请日：2003-08-28
申请人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

8. 发明申请

US20050145954A1 STRUCTURES AND METHODS FOR MAKING STRAINED MOSFETS 有权
标题翻译：制造应变MOSFET的结构和方法
公开(公告)号：US20050145954A1
公开(公告)日：2005-07-07
申请号：US10707690
申请日：2004-01-05
申请人： Huilong Zhu , Steven Bedell , Bruce Doris , Ying Zhang
发明人： Huilong Zhu , Steven Bedell , Bruce Doris , Ying Zhang
IPC分类号： H01L21/20 , H01L21/336 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block. Accordingly, a semiconductor device having a strained Si fin vertically oriented on a non-conductive substrate may be formed where the strained Si film is oriented such that it may form a channel of small dimensions allowing access to both sides and top in order to from single gate, double gate, or more gate MOSFETs and finFETs with a channel having a reduced number of defects and/or reduced dimensions.
摘要翻译：提供了提供具有减小的缺陷的应变Si膜的方法和装置，其中应变Si膜在非导电基板的表面上形成垂直取向的翅片。应变Si膜或翅片可以形成具有相对较小尺寸的半导体通道，同时也具有很少的缺陷。应变Si翅片通过在弛豫的SiGe块的一侧生长Si而形成。可以在应变Si膜的表面上形成诸如氧化物，高“k”材料或两者的组合的电介质栅极。另外，在基本上不影响应变Si膜中的应力的情况下，可以去除弛豫的SiGe块，以允许在松弛的SiGe块先前占据的表面上形成第二栅极氧化物。因此，可以形成具有垂直取向在非导电衬底上的应变Si鳍片的半导体器件，其中应变Si膜被定向成使得其可以形成允许接近两侧和顶部的小尺寸的通道，以便从单个栅极，双栅极或更多栅极MOSFET和finFET，沟道具有减少的缺陷数量和/或减小的尺寸。

9. 发明申请

US20080090366A1 Hybrid SOI-Bulk Semiconductor Transistors 失效
标题翻译：混合SOI-体半导体晶体管
公开(公告)号：US20080090366A1
公开(公告)日：2008-04-17
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

10. 发明申请

US20070181930A1 Structure and method of making double-gated self-aligned finfet having gates of different lengths 有权
标题翻译：制作具有不同长度的门的双门控自对准finfet的结构和方法
公开(公告)号：US20070181930A1
公开(公告)日：2007-08-09
申请号：US10711182
申请日：2004-08-31
申请人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
发明人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
摘要翻译：提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸，所述主体具有与所述第一侧相对的第一侧和第二侧。门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。在一个实施例中，第一栅极和第二栅极彼此电隔离。在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

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