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61. 发明申请

US20080151679A1 Synchronous semiconductor memory device 有权
公开(公告)号：US20080151679A1
公开(公告)日：2008-06-26
申请号：US12072600
申请日：2008-02-26
申请人： Kyoung-Nam Kim , Sang-Hee Kang
发明人： Kyoung-Nam Kim , Sang-Hee Kang
IPC分类号： G11C8/18
CPC分类号： G11C7/1072
摘要： A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.

62. 发明申请

US20080122502A1 Delay locked loop circuit for preventing malfunction caused by change of power supply voltage 有权
标题翻译：延迟锁定环电路，用于防止由电源电压变化引起的故障
公开(公告)号：US20080122502A1
公开(公告)日：2008-05-29
申请号：US11647219
申请日：2006-12-29
申请人： Kyoung-Nam Kim
发明人： Kyoung-Nam Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0814
摘要： A Delay Locked Loop (DLL) circuit prevents a malfunction caused by a change of a power supply voltage, and includes a first and a second delay lines and a first and a second signal processors for controlling the first and the second delay lines, and turns off the second signal processor after DLL locking. The DLL circuit further includes a phase comparator for generating a comparison signal notifying which of phases of a first clock signal of the first delay line and a second clock signal of the second delay line precedes the other, and a signal selector for inputting an output of the second signal processor to the second delay line before the DLL locking, and inputting the comparison signal of the phase comparator to the second delay line after the DLL locking.
摘要翻译：延迟锁定回路（DLL）电路防止由电源电压变化引起的故障，并且包括第一和第二延迟线以及用于控制第一和第二延迟线的第一和第二信号处理器，并且转动关闭第二个信号处理器后DLL锁定。 DLL电路还包括相位比较器，用于产生比较信号，该比较信号通知第一延迟线的第一时钟信号的相位和第二延迟线的第二时钟信号的哪一个相位在另一个之前的相位;以及信号选择器，用于输入第二信号处理器在DLL锁定之前到第二延迟线，并且在DLL锁定之后将相位比较器的比较信号输入到第二延迟线。

63. 发明授权

US07358784B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US07358784B2
公开(公告)日：2008-04-15
申请号：US11528281
申请日：2006-09-28
申请人： Kyoung-Nam Kim , Hwang Hur
发明人： Kyoung-Nam Kim , Hwang Hur
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/0814 , H03L7/087
摘要： A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and second clocks and a reset control block for resetting the delay locked loop if a phase difference between the first and second clocks is over a predetermined amount after the delay locked loop achieves a delay locking state.
摘要翻译：如果延迟锁定环路的延迟块的输出之间的相位差超过延迟锁定状态之后的预定量，则能够进行占空比补偿的延迟锁定环路复位。延迟锁定环包括用于接收第一和第二时钟的占空比补偿器和用于在延迟锁定环实现延迟锁定之后第一和第二时钟之间的相位差超过预定量的复位控制块州。

64. 发明授权

US07280422B2 BLEQ driving circuit in semiconductor memory device 有权
公开(公告)号：US07280422B2
公开(公告)日：2007-10-09
申请号：US11019496
申请日：2004-12-23
申请人： Kyoung-Nam Kim , Kang-Seol Lee
发明人： Kyoung-Nam Kim , Kang-Seol Lee
IPC分类号： G11C7/12
CPC分类号： G11C11/4094
摘要： A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply voltage, a BLEQ driver for generating the equalization signal by using the second boosted voltage in response to an equalization command and providing the equalization signal to a precharge unit, an equalizer and an I/O switch module. By using the second boosted voltage VPUP, which is lower than a first boosted voltage and higher than the supply voltage, as the equalization signal to be provided to gates of transistors for precharging a low power device to a precharge voltage level, it is possible to save current that a voltage pump consumes and satisfy a constant tRP.

65. 发明授权

US07227805B2 Semiconductor memory device having a global data bus 有权
公开(公告)号：US07227805B2
公开(公告)日：2007-06-05
申请号：US11125447
申请日：2005-05-09
申请人： Kyoung-Nam Kim , Seok-Cheol Yoon
发明人： Kyoung-Nam Kim , Seok-Cheol Yoon
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C8/10 , G11C11/4093
摘要： There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, it is easy to compensate it relying on the specific rule. The present invention proposes a scheme that classifies data transmission units corresponding to each bank into plural groups, each group having some continuous data transmission units, and makes bus lines of the global data bus to be arranged alternately for each group. In other words, the global data bus line arrangement scheme suggested by the present invention may be defined as grouped alternate arrangement scheme. In this case, the overlap interval between adjacent global data bus lines can be reduced largely and skew problem by lines can also be solved.

66. 发明申请

US20070070676A1 Pipe latch device of semiconductor memory device 有权
标题翻译：半导体存储器件的锁闩装置
公开(公告)号：US20070070676A1
公开(公告)日：2007-03-29
申请号：US11477384
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
摘要翻译：管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

67. 发明申请

US20070069795A1 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US20070069795A1
公开(公告)日：2007-03-29
申请号：US11477591
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

68. 发明申请

US20070069781A1 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US20070069781A1
公开(公告)日：2007-03-29
申请号：US11528281
申请日：2006-09-28
申请人： Kyoung-Nam Kim , Hwang Hur
发明人： Kyoung-Nam Kim , Hwang Hur
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/0814 , H03L7/087
摘要： A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and second clocks and a reset control block for resetting the delay locked loop if a phase difference between the first and second clocks is over a predetermined amount after the delay locked loop achieves a delay locking state.
摘要翻译：如果延迟锁定环路的延迟块的输出之间的相位差超过延迟锁定状态之后的预定量，则能够进行占空比补偿的延迟锁定环路复位。延迟锁定环包括用于接收第一和第二时钟的占空比补偿器和用于在延迟锁定环实现延迟锁定之后第一和第二时钟之间的相位差超过预定量的复位控制块州。

69. 发明申请

US20060171497A1 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
公开(公告)号：US20060171497A1
公开(公告)日：2006-08-03
申请号：US11320847
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03D3/24
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.

70. 发明授权

US08644092B2 Multi-chip package and method of operating the same 有权
标题翻译：多芯片封装和操作方法相同
公开(公告)号：US08644092B2
公开(公告)日：2014-02-04
申请号：US13243223
申请日：2011-09-23
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/06
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information.
摘要翻译：半导体存储器件包括：存储单元阵列，包括用于存储数据的第一存储器单元和用于存储芯片识别信息的第二存储单元;数据比较电路，用于比较输入数据和第一存储单元的存储数据，并输出比较数据和输出电路，被配置为输出从数据比较电路并行接收的比较数据。根据基于芯片ID信息生成的使能信号，通过选择的一个输出电路输出比较数据。

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