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1. 发明授权

US08143927B2 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US08143927B2
公开(公告)日：2012-03-27
申请号：US13091544
申请日：2011-04-21
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03K5/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

2. 发明授权

US07622973B2 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US07622973B2
公开(公告)日：2009-11-24
申请号：US11477591
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03K5/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：提供了一种脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

3. 发明授权

US07629822B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07629822B2
公开(公告)日：2009-12-08
申请号：US12078095
申请日：2008-03-27
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

4. 发明授权

US07368964B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07368964B2
公开(公告)日：2008-05-06
申请号：US11320847
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

5. 发明申请

US20070069795A1 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US20070069795A1
公开(公告)日：2007-03-29
申请号：US11477591
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

6. 发明申请

US20060171497A1 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
公开(公告)号：US20060171497A1
公开(公告)日：2006-08-03
申请号：US11320847
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03D3/24
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.

7. 发明授权

US07961021B2 Pulse control device 有权
标题翻译：脉冲控制装置
公开(公告)号：US07961021B2
公开(公告)日：2011-06-14
申请号：US12579705
申请日：2009-10-15
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03K5/04
CPC分类号： G06F1/04 , H03K5/1565 , H03K2005/00091
摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
摘要翻译：维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟的延迟细胞增加或减少。

8. 发明申请

US20080211553A1 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
公开(公告)号：US20080211553A1
公开(公告)日：2008-09-04
申请号：US12078095
申请日：2008-03-27
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.

9. 发明授权

US08063681B2 Semiconductor integrated circuit and method of controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US08063681B2
公开(公告)日：2011-11-22
申请号：US12915830
申请日：2010-10-29
申请人： Kyoung-Nam Kim
发明人： Kyoung-Nam Kim
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , H03L7/0812
摘要： A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.
摘要翻译：半导体集成电路包括DLL控制块，其被配置为通过在使能使能信号和阈值相位差检测信号被使能的预定时间期间检测相位检测信号的电压电平的变化来启用或禁用更新使能信号，以及延迟锁定环（DLL）电路，被配置为通过延迟和驱动参考时钟信号来产生输出时钟信号，并且响应于更新使能信号控制参考时钟信号的延迟量的变化的频率。

10. 发明授权

US07848163B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07848163B2
公开(公告)日：2010-12-07
申请号：US11824359
申请日：2007-06-29
申请人： Kyoung-Nam Kim , Young-Jun Ku , Hoon Choi
发明人： Kyoung-Nam Kim , Young-Jun Ku , Hoon Choi
IPC分类号： G11C11/063
CPC分类号： G11C7/22 , G11C7/222
摘要： A semiconductor memory device includes: a delay locked loop (DLL) clock buffer for buffering a system clock in response to the a buffer enable signal; a DLL circuit for generating a delay locked loop (DLL) clock by performing a delay locking operation using the buffered system clock; and a DLL clock buffer controller for generating the buffer enable signal in response to a code signal and a clock enable signal, the code signal containing information about whether to perform the delay locking operation.
摘要翻译：半导体存储器件包括：响应于缓冲器使能信号缓冲系统时钟的延迟锁定环（DLL）时钟缓冲器; 一个DLL电路，用于通过使用缓冲的系统时钟执行延迟锁定操作来产生延迟锁定环（DLL）时钟; 以及DLL时钟缓冲器控制器，用于响应于代码信号和时钟使能信号产生缓冲器使能信号，所述代码信号包含关于是否执行延迟锁定操作的信息。

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