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1. 发明授权

US08644092B2 Multi-chip package and method of operating the same 有权
标题翻译：多芯片封装和操作方法相同
公开(公告)号：US08644092B2
公开(公告)日：2014-02-04
申请号：US13243223
申请日：2011-09-23
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/06
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information.
摘要翻译：半导体存储器件包括：存储单元阵列，包括用于存储数据的第一存储器单元和用于存储芯片识别信息的第二存储单元;数据比较电路，用于比较输入数据和第一存储单元的存储数据，并输出比较数据和输出电路，被配置为输出从数据比较电路并行接收的比较数据。根据基于芯片ID信息生成的使能信号，通过选择的一个输出电路输出比较数据。

2. 发明申请

US20100302827A1 CODE ADDRESS MEMORY (CAM) CELL READ CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA OF CAM CELL 失效
标题翻译：代码地址存储器（CAM）读取半导体存储器件的控制电路和读取CAM单元的数据的方法
公开(公告)号：US20100302827A1
公开(公告)日：2010-12-02
申请号：US12650980
申请日：2009-12-31
申请人： Kyoung Nam KIM , Beom Ju Shin
发明人： Kyoung Nam KIM , Beom Ju Shin
IPC分类号： G11C15/00 , G11C7/00 , G11C7/10
CPC分类号： G11C15/046 , G11C15/00
摘要： A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.
摘要翻译：半导体存储器件的代码地址存储器（CAM）单元读取控制电路包括：CAM单元读取电路，被配置为读取存储在CAM单元中的数据并输出读取的数据;内部延迟电路，被配置为延迟外部输入的复位信号并且产生多个内部命令信号，以及信号生成单元，被配置为响应于内部命令信号而生成内部就绪/忙信号。内部就绪/忙信号在外部输入复位信号复位CAM单元读取电路后产生。

3. 发明授权

US08344754B2 Multi-chip package 有权
标题翻译：多芯片封装
公开(公告)号：US08344754B2
公开(公告)日：2013-01-01
申请号：US12982544
申请日：2010-12-30
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： H03K17/16 , H03K19/0175 , H03B1/00
CPC分类号： H03K19/00346
摘要： A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.
摘要翻译：多芯片封装包括与I / O焊盘并联耦合的多个芯片和包括在每个芯片中的输出驱动器电路，并被配置为将输出数据发送到I / O焊盘。输出驱动电路的驱动力是根据表示正在激活的芯片数量的堆栈信息进行控制的。

4. 发明申请

US20120140577A1 MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME 有权
标题翻译：多芯片封装及其操作方法
公开(公告)号：US20120140577A1
公开(公告)日：2012-06-07
申请号：US13243223
申请日：2011-09-23
申请人： Kyoung Nam KIM , Beom Ju Shin
发明人： Kyoung Nam KIM , Beom Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information.
摘要翻译：半导体存储器件包括：存储单元阵列，包括用于存储数据的第一存储器单元和用于存储芯片识别信息的第二存储单元;数据比较电路，用于比较输入数据和第一存储单元的存储数据，并输出比较数据和输出电路，被配置为输出从数据比较电路并行接收的比较数据。根据基于芯片ID信息生成的使能信号，通过选择的一个输出电路输出比较数据。

5. 发明授权

US08233334B2 Code address memory (CAM) cell read control circuit of semiconductor memory device and method of reading data of CAM cell 失效
标题翻译：半导体存储器件的代码地址存储器（CAM）单元读取控制电路和读取CAM单元的数据的方法
公开(公告)号：US08233334B2
公开(公告)日：2012-07-31
申请号：US12650980
申请日：2009-12-31
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C15/046 , G11C15/00
摘要： A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.
摘要翻译：半导体存储器件的代码地址存储器（CAM）单元读取控制电路包括：CAM单元读取电路，被配置为读取存储在CAM单元中的数据并输出读取的数据;内部延迟电路，被配置为延迟外部输入的复位信号并且产生多个内部命令信号，以及信号生成单元，被配置为响应于内部命令信号而生成内部就绪/忙信号。内部就绪/忙信号在外部输入复位信号复位CAM单元读取电路后产生。

6. 发明申请

US20100287337A1 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100287337A1
公开(公告)日：2010-11-11
申请号：US12700400
申请日：2010-02-04
申请人： Beom Ju Shin , Kyoung Nam Kim
发明人： Beom Ju Shin , Kyoung Nam Kim
IPC分类号： G06F12/00 , G06F1/04
CPC分类号： G11C16/20 , G11C15/00 , G11C16/10
摘要： A nonvolatile memory device has a memory cell array including a memory cell group for storing option information, and a controller configured to wait for a preset period of time after a command for loading the option information has been received before performing an operation of loading the option information.
摘要翻译：非易失性存储器件具有包括用于存储选项信息的存储单元组的存储单元阵列，以及控制器，被配置为在执行加载选项的操作之前，在接收到用于加载选项信息的命令之后等待预设的时间段信息。

7. 发明授权

US08437203B2 Nonvolatile memory apparatus and method for processing configuration information thereof 有权
标题翻译：非易失性存储装置及其配置信息的处理方法
公开(公告)号：US08437203B2
公开(公告)日：2013-05-07
申请号：US12983138
申请日：2010-12-31
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C16/20
摘要： A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period.
摘要翻译：非易失性存储装置包括存储装置，具有用于存储第一配置数据组的配置信息存储块和比第一配置数据组少的位的第二配置数据组，配置信息处理电路被配置为确定第一配置数据组的大部分配置数据组在上电操作的第一周期期间从存储器件输出，并且在第一周期之后的第二周期期间确定从存储器件输出的大部分第二配置数据组。

8. 发明申请

US20120032706A1 MULTI-CHIP PACKAGE 有权
标题翻译：多芯片包装
公开(公告)号：US20120032706A1
公开(公告)日：2012-02-09
申请号：US12982544
申请日：2010-12-30
申请人： Kyoung Nam KIM , Beom Ju Shin
发明人： Kyoung Nam KIM , Beom Ju Shin
IPC分类号： H03K3/00
CPC分类号： H03K19/00346
摘要： A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.
摘要翻译：多芯片封装包括与I / O焊盘并联耦合的多个芯片和包括在每个芯片中的输出驱动器电路，并被配置为将输出数据发送到I / O焊盘。输出驱动电路的驱动力是根据表示正在激活的芯片数量的堆栈信息进行控制的。

9. 发明申请

US20100284230A1 METHOD OF OPERATING NONVOLATILE MEMORY DEVICE 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20100284230A1
公开(公告)日：2010-11-11
申请号：US12701877
申请日：2010-02-08
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off the supply of the variable voltage to the first bit line, after the first time period, and precharging the first bit line to a second voltage level through a sense node of the selected page buffer, which is in a precharge state, evaluating a voltage of the first bit line, after the precharging of the first bit line, so that the voltage of the first bit line is shifted according to a program state of the selected memory cell, and sensing the voltage of the evaluated first bit line and latching data in the selected memory cell.
摘要翻译：一种操作非易失性存储器件的方法包括：将第一电压电平的可变电压提供给所选择的页面缓冲器，并将可变电压提供给第一位线，该第一位线耦合到第一时间段中被选择用于数据读取的所选存储器单元在第一时间段之后切断对第一位线的可变电压的供应，并且通过处于预充电状态的所选择的页面缓冲器的感测节点将第一位线预充电到第二电压电平，评估第一位线的电压在第一位线的预充电之后，使得第一位线的电压根据所选存储单元的编程状态而偏移，并且感测所评估的第一位线的电压，以及在所选存储单元中锁存数据。

10. 发明授权

US06862248B2 Method for masking ringing in DDR SDRAM 有权
标题翻译：屏蔽DDR SDRAM振铃的方法
公开(公告)号：US06862248B2
公开(公告)日：2005-03-01
申请号：US10736824
申请日：2003-12-16
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C11/40 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1093 , G11C7/1078
摘要： A method for masking a ringing in a DDR SDRAM comprises in a write mode, generating first and second synchronizing signals by means of a DQS signal inputted from an exterior circuit, in order to synchronize input data, latching data in odd sequences from among the inputted data, which are sequentially inputted, at a rising edge of the first synchronizing signal, and latching data in even sequences from among the data, which are sequentially inputted, at a rising edge of the second synchronizing signal, aligning the data in odd sequences and the data in even sequences at a falling edge of the DQS signal so that the odd and even sequenced data has the same synchronized timing, and blocking activation of the second synchronizing signal by means of a first control signal, the a first control signal being synchronized with the falling edge of the last valid DQS signal that is normally inputted, so as to enable the blocking step and thereby masking the ringing phenomenon. In the method for masking the ringing phenomenon, the point at which the DIS_DSB signal is enabled in a low state is synchronized with the last falling edge of the normal DQS signal, and therefore the DSF2 signal is disabled.
摘要翻译：用于屏蔽DDR SDRAM中的振铃的方法包括在写入模式中，通过从外部电路输入的DQS信号产生第一和第二同步信号，以便同步输入数据，从输入的奇数序列中锁存数据在第一同步信号的上升沿依次输入的数据，以及从顺序地输入的数据中的偶数序列中的数据锁存在第二同步信号的上升沿，以奇数序列对准数据，在DQS信号的下降沿以均匀顺序的数据，使得奇数和偶校序数据具有相同的同步定时，以及借助于第一控制信号阻止第二同步信号的激活，第一控制信号被同步通常输入最后一个有效的DQS信号的下降沿，以便能够进行阻塞步骤，从而掩盖振铃现象。在屏蔽振铃现象的方法中，DIS_DSB信号在低电平状态下使能的点与正常DQS信号的最后一个下降沿同步，因此DSF2信号被禁止。

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