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61. 发明申请

US20090177846A1 Retry Mechanism 有权
标题翻译：重试机制
公开(公告)号：US20090177846A1
公开(公告)日：2009-07-09
申请号：US12408410
申请日：2009-03-20
申请人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
发明人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F12/00 , G06F3/00 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0831 , G06F13/362 , G06F13/4213 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.
摘要翻译：接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应。控制单元还被配置为提供具有重试响应的第二事务的标识符。

62. 发明申请

US20090055568A1 Non-blocking Address Switch with Shallow Per Agent Queues 有权
标题翻译：非阻塞地址交换机与每个代理队列相邻
公开(公告)号：US20090055568A1
公开(公告)日：2009-02-26
申请号：US12263255
申请日：2008-10-31
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/14
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

63. 发明申请

US20080307276A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20080307276A1
公开(公告)日：2008-12-11
申请号：US11760566
申请日：2007-06-08
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G11C29/04 , G06F12/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

64. 发明授权

US07296122B2 Flexible probe/probe response routing for maintaining coherency 有权
标题翻译：灵活的探头/探头响应路由保持一致性
公开(公告)号：US07296122B2
公开(公告)日：2007-11-13
申请号：US10628715
申请日：2003-07-28
申请人： James B. Keller , Dale E. Gulick
发明人： James B. Keller , Dale E. Gulick
IPC分类号： G06F12/14 , G06F12/16
CPC分类号： G06F12/0815 , G06F12/0817
摘要： A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data). On the other hand, for write transactions (in which data is being updated in memory at the target node of the transaction), the probe commands may specify the target of the transaction as the receiving node. In this manner, the target may determine when to commit the write data to memory and may receive any dirty data to be merged with the write data.
摘要翻译：计算机系统可以包括多个处理节点，其中的一个或多个处理节点可以耦合到可以形成分布式存储器系统的分离的存储器。处理节点可以包括高速缓存，并且计算机系统可以保持高速缓存和分布式存储器系统之间的一致性。特别地，计算机系统可以实现灵活的探测命令/响应路由方案。该方案可以采用探测命令中的指示，该指示标识接收节点以接收探测响应。例如，可以包括指示目标或事务源应该接收对应于事务的探测响应的探测命令。探测命令可以将事务的来源指定为读取事务的接收节点（使得脏数据从存储脏数据的节点传送到源节点）。另一方面，对于写入事务（其中数据正在事务的目标节点的存储器中更新），探测命令可以将事务的目标指定为接收节点。以这种方式，目标可以确定何时将写入数据提交到存储器，并且可以接收要与写入数据合并的任何脏数据。

65. 发明授权

US06952791B2 Method and circuit for initializing a de-skewing buffer in a clock forwarded system 失效
标题翻译：在时钟转发系统中初始化去偏移缓冲区的方法和电路
公开(公告)号：US06952791B2
公开(公告)日：2005-10-04
申请号：US10044549
申请日：2002-01-11
申请人： James B. Keller , Daniel W. Dobberpuhl
发明人： James B. Keller , Daniel W. Dobberpuhl
IPC分类号： G06F5/10 , H04L7/00 , H04L7/10 , G06F1/04
CPC分类号： G06F5/10 , G06F2205/104 , H04L7/00 , H04L7/0008 , H04L7/005 , H04L7/10
摘要： A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may use a write pointer and a read pointer which may be clocked by two different clocks allowing independent write and read accesses to the buffer. In an initialization mode, a predetermined pattern of data may be written into an entry in the buffer. In one embodiment, a logic circuit may detect the predetermined pattern of data and may cause the value of the write pointer to be captured. A synchronizing circuit may synchronize an indication that the predetermined pattern of data has been detected to the clock used by the read pointer. The synchronizer circuit may then provide a initialize signal to the read pointer which stores the captured write pointer value into the read pointer. This captured write pointer value becomes the initial value of the read pointer, effectively offsetting the read pointer from the write pointer.
摘要翻译：一种用于在时钟转发系统中初始化缓冲器的方法和电路。缓冲区被配置为临时存储在时钟转发接口上接收的输入数据。缓冲器可以使用写指针和读指针，读指针可以由两个不同的时钟计时，从而允许对缓冲器的独立的写和读访问。在初始化模式中，可以将预定的数据模式写入缓冲器中的条目。在一个实施例中，逻辑电路可以检测预定的数据模式，并且可以引起写指针的值被捕获。同步电路可以使已经检测到预定数据模式的指示与读指针使用的时钟同步。同步器电路然后可以向读指针提供初始化信号，该指针将捕获的写指针值存储到读指针中。这个捕获的写指针值成为读指针的初始值，有效地将读指针从写指针中移除。

66. 发明授权

US06938094B1 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation 有权
标题翻译：虚拟通道和相应的缓冲区分配，用于无死锁的计算机系统操作
公开(公告)号：US06938094B1
公开(公告)日：2005-08-30
申请号：US09399281
申请日：1999-09-17
申请人： James B. Keller , Derrick R. Meyer
发明人： James B. Keller , Derrick R. Meyer
IPC分类号： G06F12/08 , G06F13/38 , G06F15/173 , G06F15/177 , H04L12/28
CPC分类号： G06F15/17381
摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, each virtual channel may be assigned control packet buffers and data packet buffers. Control packets may be substantially smaller in size, and may occur more frequently than data packets. By providing separate buffers, buffer space may be used efficiently. If a control packet which does not specify a data packet is received, no data packet buffer space is allocated. If a control packet which does specify a data packet is received, both control packet buffer space and data packet buffer space is allocated.
摘要翻译：计算机系统采用虚拟通道并为虚拟通道分配不同的资源。没有逻辑/协议相关冲突的数据包被分组成虚拟通道。因此，在分离的虚拟通道中的分组之间发生逻辑冲突。虚拟通道内的数据包可能共享资源（从而遇到资源冲突），但不同虚拟通道内的数据包可能不共享资源。由于可能遇到资源冲突的数据包不会发生逻辑冲突，并且由于可能遇到逻辑冲突的数据包不会遇到资源冲突，因此可能会实现无死锁操作。另外，每个虚拟信道可以被分配控制分组缓冲器和数据分组缓冲器。控制分组的大小可能会更小，并且可能比数据分组更频繁地发生。通过提供单独的缓冲区，可以有效地使用缓冲区空间。如果接收到不指定数据分组的控制分组，则不分配数据分组缓冲空间。如果接收到指定数据分组的控制分组，则分配控制分组缓冲区空间和数据分组缓冲区空间。

67. 发明授权

US06745272B2 System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system 有权
标题翻译：增加带宽的系统和方法，用于将有序交易发布到分布式通信系统中
公开(公告)号：US06745272B2
公开(公告)日：2004-06-01
申请号：US09826262
申请日：2001-04-04
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
IPC分类号： G06F1300
CPC分类号： H04L1/1671
摘要： A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.
摘要翻译：一种将一对有序请求的第二请求发布到分布式相干通信结构中的方法和系统。有序对的第一个请求被发布到相干通信结构中，并被引导到第一个目标。将第二个请求发送到相干通信结构中停止，直到第一个目标接收并订购第一个请求并发送确认该响应的响应。

68. 发明授权

US06728841B2 Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system 有权
标题翻译：在多处理计算机系统中的存储器读取操作期间节省系统存储器带宽
公开(公告)号：US06728841B2
公开(公告)日：2004-04-27
申请号：US10002753
申请日：2001-10-31
申请人： James B. Keller
发明人： James B. Keller
IPC分类号： G06F1300
CPC分类号： G06F12/0813
摘要： A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. The target node transmits a read response to the source node containing the requested data and also concurrently transmits a probe command to one or more of the remaining nodes in the multiprocessing computer system. In response to the probe command each remaining processing node checks whether the processing node has a cached copy of the requested data. If a processing node, other than the source and the target nodes, finds a modified cached copy of the designated memory location, that processing node responds with a memory cancel response sent to the target node and a read response sent to the source node. The read response contains the modified cache block containing the requested data, and the memory cancel response causes the target node to abort further processing of the memory read command, and to stop transmission of the read response, if the target node hasn't transmitted the read response yet. The memory cancel message thus attempts to avoid relatively lengthy and time-consuming system memory accesses when the system memory has a stale data.
摘要翻译：描述了在多处理计算机系统中的存储器读取操作期间节省系统存储器带宽的消息传递方案。源处理节点向目标处理节点发送存储器读取命令，以从与目标处理节点相关联的系统存储器中的指定存储器位置读取数据。目标节点向包含所请求数据的源节点发送读取响应，并且还向多处理计算机系统中的一个或多个剩余节点发送探测命令。响应于探测命令，每个剩余的处理节点检查处理节点是否具有所请求数据的缓存副本。如果除了源节点和目标节点之外的处理节点找到指定的存储器位置的经修改的缓存副本，则该处理节点以发送到目标节点的存储器取消响应和发送到源节点的读取响应进行响应。读取响应包含包含所请求数据的经修改的高速缓存块，并且存储器取消响应导致目标节点中止对存储器读取命令的进一步处理，并且停止读取响应的传输，如果目标节点尚未发送阅读回应。因此，当系统存储器具有陈旧数据时，存储器取消消息尝试避免相对冗长且耗时的系统存储器访问。

69. 发明授权

US06651144B1 Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state 失效
标题翻译：用于使用外部确认信号开发多处理器高速缓存控制协议以将高速缓存设置为脏状态的方法和装置
公开(公告)号：US06651144B1
公开(公告)日：2003-11-18
申请号：US09099384
申请日：1998-06-18
申请人： Rahul Razdan , James B. Keller , Richard E. Kessler
发明人： Rahul Razdan , James B. Keller , Richard E. Kessler
IPC分类号： G06F1200
CPC分类号： G06F12/0815 , G06F12/0817
摘要： A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a memory management system responsive to the set-dirty request. The memory management system receives the set-dirty request, determines the acknowledgment based on contents of the plurality of caches and the main memory according to a cache protocol and sends the acknowledgment to the external unit in response to the set-dirty request. The acknowledgment will either grant permission or deny permission to set the block to the dirty state.
摘要翻译：计算机系统包括管理高速缓存的外部单元，该高速缓冲存储器根据要修改的高速缓存中的块的相干状态生成设置脏请求。仅当响应于设置的脏请求从存储器管理系统接收到确认授权许可时，外部单元才修改高速缓存块。存储器管理系统接收设置脏请求，根据高速缓存协议基于多个高速缓存和主存储器的内容确定确认，并响应于设置脏请求将确认发送到外部单元。该确认将授予权限或拒绝许可将块设置为脏状态。

70. 发明授权

US06647490B2 Training line predictor for branch targets 有权
标题翻译：分支目标的训练线预测
公开(公告)号：US06647490B2
公开(公告)日：2003-11-11
申请号：US09419832
申请日：1999-10-14
申请人： James B. Keller , Puneet Sharma , Keith R. Schakel , Francis M. Matus
发明人： James B. Keller , Puneet Sharma , Keith R. Schakel , Francis M. Matus
IPC分类号： G06F938
CPC分类号： G06F9/30149 , G06F9/30054 , G06F9/3806 , G06F9/3808 , G06F9/3816 , G06F9/382
摘要： A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Additionally, each entry may include a link to another entry storing instruction pointers to the next instructions within the predicted instruction stream, and a next fetch address corresponding to the first instruction within the next entry. The next fetch address may be provided to the instruction cache to fetch the corresponding instruction bytes. If the terminating instruction within the entry is a branch instruction, the line predictor is trained with respect to the next fetch address (and next index within the line predictor, which provides the link to the next entry). As line predictor entries are created, a set of branch predictors may be accessed to provide an initial next fetch address and index. The initial training is verified by accessing the branch predictors at each fetch of the line predictor entry, and updated as dictated by the state of the branch predictors at each fetch.
摘要翻译：行预测器缓存对齐信息的指令。响应于每个提取地址，行预测器提供从取指址开始的指令的对齐信息，以及该指令之后的一个或多个附加指令。线预测器可以包括具有多个条目的存储器，每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。此外，每个条目可以包括链接到存储指向预测指令流中的下一个指令的指令的另一个条目，以及对应于下一条目中的第一指令的下一个提取地址。可以将下一个提取地址提供给指令高速缓存以获取对应的指令字节。如果条目中的终止指令是分支指令，则线路预测器相对于下一个提取地址（以及行预测器中的下一个索引（其提供到下一个条目的链接））进行训练。当创建线预测值条目时，可以访问一组分支预测器来提供初始的下一个提取地址和索引。通过在行预测器条目的每次获取时访问分支预测器来验证初始训练，并且根据每次获取时分支预测器的状态来更新初始训练。

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